Germanium Oxide Capping Layer for Low-Leakage Gate Structures
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Solution Overview
Problem
Challenges arise during the scaling-down process of semiconductor devices, including issues with leakage, trap density, and resistance, which affect quality, yield, performance, and reliability.
Innovation Solution
The semiconductor device incorporates a capping layer made of germanium oxide, which reduces leakage and trap density, and a conductive layer made of germanium to lower resistance, enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional materials are used for capping and conductive layers during device scaling, then manufacturing simplicity is maintained, but leakage increases and trap density increases
Solution Approach 1:
The patent employs a composite material structure where a germanium oxide capping layer is combined with a germanium conductive layer. The germanium oxide layer provides superior leakage prevention and trap density reduction properties, while the germanium layer offers high conductivity. This composite approach resolves the contradiction by achieving enhanced reliability through material composition rather than structural complexity.
Solution Approach 2:
The patent changes the material parameters by substituting conventional capping materials (such as silicon oxide) with germanium oxide, and conventional conductive materials with germanium. This parameter change in material composition enables superior electrical characteristics including reduced leakage and reduced trap density, while maintaining a relatively simple layered structure suitable for scaled devices.
2Reliability
If conventional conductive materials are used, then manufacturing simplicity is maintained, but resistance increases
Solution Approach 1:
The patent uses a composite structure with a germanium conductive layer that provides high conductivity and low resistance. The germanium material inherently offers superior electrical transport properties compared to conventional conductive materials, enabling reduced resistance while maintaining compatibility with existing manufacturing processes for depositing thin films.
Solution Approach 2:
The patent changes the conductive material parameter from conventional materials (such as tungsten or copper) to germanium, which has superior electrical conductivity. This material substitution reduces resistance and improves device performance while the deposition process remains consistent with existing semiconductor manufacturing capabilities.
3Productivity
If device dimensions are scaled down, then computing ability increases, but leakage increases and trap density increases
Solution Approach 1:
The patent addresses scaling challenges by implementing a composite layer structure with germanium oxide capping layer and germanium conductive layer. This composite material approach provides enhanced control over leakage and trap density at scaled dimensions, enabling continued improvement in computing ability while maintaining reliability through superior material properties that are particularly effective at small feature sizes.
Data Source
AI summary
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a capping mask layer positioned on the substrate; a first gate insulating layer positioned along the capping mask layer, inwardly positioned in the substrate, and including a U-shaped cross-sectional profile; a first work function layer positioned on the first gate insulating layer; a first conductive layer positioned on the first work function layer; and a first capping layer positioned on the first conductive layer. The first capping layer includes germanium oxide. A top surface of the first capping layer and a top surface of the capping mask layer are substantially coplanar.