III-V Substrate Passivation with Germanium Layer
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Solution Overview
Problem
The effective electrical passivation of III-V semiconductor materials is challenging due to high density of defect states at the III-V/oxide interfaces, leading to poor electrical performance in devices like MOSFETs and HEMTs, as the Fermi level is pinned, and existing methods either limit integration options or fail to control stress and electron counting.
Innovation Solution
A method involving the growth of a thin epitaxial Germanium passivation layer on III-V substrates with specific crystal orientations, such as (110), which balances electron counting and reduces surface stress, followed by partial oxidation and etching, allowing for the deposition of high-k dielectric layers and improving band alignment for enhanced device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If surface passivation using sulfur compounds or surface cleaning using hydrogen or nitrogen plasma is applied, then surface Fermi level pinning is reduced, but the integration options are limited and the electrical performances remain poor
Solution Approach 1:
The patent changes the material parameter by using amorphous silicon instead of sulfur compounds or plasma treatments, and controls the thickness parameter (5-50 nm) to achieve both Fermi level depinning and compatibility with standard CMOS integration processes
Solution Approach 2:
The amorphous silicon layer acts as an intermediary between the III-V substrate and the high-k dielectric layer, providing both surface passivation and a compatible interface for subsequent dielectric deposition processes
2Adaptability or versatility
If an amorphous layer of silicon is deposited on top of an III-V substrate, then integration options are improved, but the stress induced in the substrate and electron-counting that govern the Fermi level pinning at the interface are not controlled
Solution Approach 1:
The patent precisely controls the thickness parameter of the amorphous silicon layer (5-50 nm) to balance stress effects and achieve proper electron-counting for Fermi level depinning, while maintaining compatibility with CMOS integration
Solution Approach 2:
The patent uses feedback by monitoring and controlling the amorphous silicon layer thickness to achieve the optimal balance between stress control and electron-counting for effective Fermi level pinning reduction
3Reliability
If a GaGdOx oxide is grown epitaxially on top of an III-V substrate, then the interface stress is minimized and Fermi level is unpinned, but the specific GaGdOx shows significant leakage and integration options are limited
Solution Approach 1:
The patent introduces an amorphous silicon intermediary layer between the III-V substrate and the high-k dielectric, which provides surface passivation and enables standard CMOS integration while avoiding the leakage problems of epitaxial GaGdOx
Solution Approach 2:
The patent changes from epitaxial growth to amorphous deposition and controls the layer thickness (5-50 nm) to achieve both Fermi level depinning and compatibility with standard integration processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in an unpinned Fermi level, reduced interface state density, and improved electrical performance by matching lattice parameters and controlling surface stress, enabling the production of advanced electronic devices with superior performance.
Implementation Method 1
growth of a thin epitaxial Germanium passivation layer on III-V substrates
Implementation Method 2
matching lattice parameters and controlling surface stress
Implementation Method 3
followed by partial oxidation and etching
Data Source
Figure 1a
Figure 1b
Figure 2
AI summary
Manufacturing an III-V engineered substrate involves providing a base substrate (I) comprising an upper layer (2) made of a first III-V compound with a <110> or a <111> crystal orientation, forming an intermediate layer (II) comprising forming at least a buffer layer (3) of a second III-V compound, wherein the intermediate layer (II) is overlying and in contact with the upper layer (2) of the base substrate. Then a pseudomorphic passivation layer (4) made of a group IV semiconductor material is grown so as to be overlying and in contact with the intermediate layer (II). This can enable an unpinned interface. The substrate surface can be smoother, implying fewer problems from surface stress. It can be used in electronic devices such as metal-oxide-semiconductor field effect transistors (MOSFETs), high electron mobility transistors (HEMTs), tunneling field effect transistors (TFETs), and optoelectronic devices.