GeSiC Floating Gate Reduces Tunneling Barrier for Faster Erase
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Solution Overview
Problem
Conventional EEPROM devices, such as flash memory, have slow erase times due to high tunneling barriers in gate oxides, which limits their speed and efficiency compared to other memory types like DRAM.
Innovation Solution
The use of a floating gate made of germanium silicon carbide (GeSiC) material, which reduces the tunneling barrier height, allowing for faster erase operations and lower erase voltages, thereby enhancing the speed and reliability of EEPROM devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate oxide is used in EEPROM devices, then the tunneling barrier height is high, but the erase time becomes slow
Solution Approach 1:
The patent changes the material composition of the floating gate from conventional polysilicon to germanium-silicon-carbide (GeSiC) alloy. This parameter change in material composition directly reduces the tunneling barrier height at the gate oxide interface, enabling faster electron tunneling during erase operations while maintaining sufficient barrier height for reliable data retention.
Solution Approach 2:
The patent employs a composite material approach by creating a GeSiC floating gate that combines germanium, silicon, and carbon elements. This composite structure provides optimized electronic properties including reduced tunneling barrier height compared to conventional materials, while maintaining the necessary electrical characteristics for EEPROM operation.
2Reliability
If large positive voltage is applied to control gate for write operation, then electrons are trapped on floating gate, but high voltage requirements increase device complexity
Solution Approach 1:
The GeSiC floating gate material modifies the tunneling characteristics to enable effective electron trapping at lower control gate voltages compared to conventional polysilicon gates. This parameter change in material composition reduces the voltage magnitude required for write operations, simplifying the voltage generation and management circuitry.
3Reliability
If large negative voltage is applied for erase operation, then electrons are driven off floating gate, but long erase time period is required
Solution Approach 1:
The patent changes the floating gate material to GeSiC, which reduces the tunneling barrier height and enables much faster electron tunneling during erase operations. This parameter change allows complete erase operations to be completed in significantly reduced time while maintaining reliable electron ejection efficiency.
Solution Approach 2:
The reduced tunneling barrier in GeSiC enables a transition in the tunneling regime, allowing electrons to tunnel through the gate oxide barrier much more rapidly during erase operations. This effective phase transition in electron transport kinetics reduces erase time from conventional slow rates to faster rates comparable to other semiconductor memory types.
4Speed
If floating gate material is changed to reduce tunneling barrier, then erase speed improves, but manufacturing precision requirements may increase
Solution Approach 1:
The GeSiC floating gate uses a composite material system where the combination of germanium, silicon, and carbon provides both the desired reduced tunneling barrier and robust manufacturing characteristics. The composite nature allows for process optimization and control that balances manufacturing precision requirements with performance benefits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in significantly faster erase times and improved operational speeds for EEPROM devices, making them more competitive with DRAMs and potentially replacing both magnetic and DRAM memory in future computer devices.
Implementation Method 1
The rate at which the electrons can be transported through the insulating gate oxide to and from the floating gate is an exponential factor of both the thickness of the insulator and of the electrical height of the insulation barrier between the substrate and the floating gate. This operation may occur through various mechanisms, such as Fowler-Nordheim (FN) tunneling.
Implementation Method 2
A large positive voltage on the control gate will draw electrons from the substrate through the gate oxide and trap them on the floating gate. The erase operation uses a large negative voltage to drive any stored electrons on the floating gate off of the gate and back into the substrate
Data Source
AI summary
The use of a germanium carbide (GeC), or a germanium silicon carbide (GeSiC) layer as a floating gate material to replace heavily doped polysilicon (poly) in fabricating floating gates in EEPROM and flash memory results in increased tunneling currents and faster erase operations. Forming the floating gate includes depositing germanium-silicon-carbide in various combinations to obtain the desired tunneling current values at the operating voltage of the memory device.