Ge/SiGe and III-V Transistor Pseudo-Substrate Integration
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Solution Overview
Problem
The formation of Ge/SiGe-channel and III-V-channel transistors on a common substrate poses challenges such as degradation in electrical carrier mobility, interface trap density, and dopant migration due to significant defect densities, which affect the performance and yield of CMOS devices.
Innovation Solution
The technique involves depositing a pseudo-substrate of Ge/SiGe or III-V material on a Si or insulator substrate, patterning it into fins, and replacing a subset of these fins with the other material, allowing for improved electrical carrier mobility and reduced dopant segregation, thereby enhancing the performance and yield of transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If Ge/SiGe and III-V materials are deposited directly on Si substrate, then both Ge/SiGe-channel and III-V-channel transistors can be formed on the same die, but significant defect densities cause degradation in electrical carrier mobility, increased interface trap density, and dopant migration
Solution Approach 1:
The patent introduces a pseudo-substrate layer composed of Ge/SiGe or III-V material as an intermediary between the Si substrate and the transistor channel materials. This pseudo-substrate serves as a buffer that reduces defect density and prevents direct interaction between the Si substrate and the sensitive channel materials, thereby maintaining electrical carrier mobility and reducing interface trap density while enabling formation of both Ge/SiGe-channel and III-V-channel transistors on the same die
Solution Approach 2:
The patent segments the transistor structure into distinct layers: Si substrate, pseudo-substrate layer, and channel material layer. This segmentation allows each layer to be optimized independently - the Si substrate provides mechanical support, the pseudo-substrate reduces defects, and the channel material provides the desired electrical properties. The pseudo-substrate acts as an intermediate layer that decouples the substrate from the channel materials, resolving the contradiction between versatility and reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved electrical carrier mobility, reduced interface trap density, and minimized dopant migration, leading to enhanced performance and yield of Ge/SiGe-channel and III-V-channel transistors in CMOS devices.
Implementation Method 1
The techniques include depositing a pseudo-substrate of Ge/SiGe or III-V material on a Si or insulator substrate
Data Source
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Figure 2C~2D
AI summary
Techniques are disclosed for forming Ge/SiGe-channel and III-V-channel transistors on the same die. The techniques include depositing a pseudo- substrate of Ge/SiGe or III-V material on a Si or insulator substrate. The pseudo-substrate can then be patterned into fins and a subset of the fins can be replaced by the other of Ge/SiGe or III-V material. The Ge/SiGe fins can be used for p-MOS transistors and the III-V material fins can be used for n-MOS transistors, and both sets of fins can be used for CMOS devices, for example. In some instances, only the channel region of the subset of fins are replaced during, for example, a replacement gate process. In some instances, some or all of the fins may be formed into or replaced by one or more nanowires or nanoribbons.