Ge/Si1-yGey Fin Preferential Oxidation for Strained Nanowire Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods fail to effectively and reliably form strained or nanowire channel regions for non-planar transistors, leading to issues such as increased off-state leakage and power consumption due to difficulties in inducing strain in free-standing Si fins and random dimensions/placement of nanowires during manufacturing.
Innovation Solution
The method involves using preferential oxidation to convert a Si fin into a Ge/Si1-yGey fin or nanowire channel, which is uniaxially compressively strained, and is self-aligned with STI regions, allowing for the formation of multigate transistors or memory cells with reduced defects and improved integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional methods are used to introduce strain in non-planar transistor channels using recess etch/raised source/drain regions on free standing Si fins, then device speed may be improved, but manufacturing reliability deteriorates due to difficulty in producing uniform strained structures
Solution Approach 1:
The patent replaces the mechanical approach of recess etching and raised source/drain region formation with a chemical oxidation approach. The Si fin is converted to Ge/Si1-yGey fin through preferential oxidation, which inherently introduces uniaxial compressive strain without requiring complex mechanical structuring operations. This substitution eliminates the manufacturing variability associated with multiple etch and deposition steps.
Solution Approach 2:
The patent changes the material composition parameter by converting pure Si fin to Ge/Si1-yGey alloy fin through oxidation. This compositional change simultaneously achieves strain introduction and improved carrier mobility, resolving the contradiction between device speed improvement and manufacturing reliability.
2Speed
If channel length is reduced to increase device speed, then gate delay decreases, but off-state leakage current increases due to threshold voltage roll-off
Solution Approach 1:
The patent uses composite Ge/Si1-yGey material in the fin structure, combining silicon with germanium oxide phases. This composite structure provides both the short channel performance needed for high speed and the strain necessary to maintain threshold voltage, thereby reducing off-state leakage while preserving device speed.
Solution Approach 2:
The oxidation process creates local variations in composition within the fin structure, with Ge-rich regions providing strain and Si-rich regions maintaining semiconductor properties. This local quality variation allows the structure to simultaneously address short channel effects and maintain high carrier mobility for fast operation.
3Ease of manufacture
If nanowires are grown by CVD using catalytic nucleation sites, then nanowire channels can be formed, but manufacturing precision deteriorates due to random dimensions and placement
Solution Approach 1:
The patent performs preliminary patterning to define precise fin locations and dimensions before oxidation. The Ge/Si1-yGey fin is formed by oxidizing a pre-patterned Si fin structure, ensuring that nanowire positions and dimensions are predetermined with high precision rather than randomly formed during growth.
Solution Approach 2:
The patent replaces the catalytic chemical vapor deposition process with a controlled oxidation process acting on a pre-formed Si fin structure. This substitution eliminates the random nucleation inherent in CVD and enables precise control over nanowire location, size, and orientation through standard semiconductor fabrication patterning techniques.
4Speed
If higher carrier mobility semiconductor materials like germanium are used to form the channel, then device speed increases, but manufacturing complexity increases due to difficulty in integrating with existing Si processes
Solution Approach 1:
The patent changes the oxidation conditions (temperature, time, atmosphere) to control the extent of Ge formation in the Si fin. By adjusting these parameters, the process produces Ge/Si1-yGey compositions optimized for carrier mobility while remaining compatible with standard CMOS fabrication processes, thus achieving high speed without excessive manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of high-performance transistors with reduced power consumption and increased integration density by forming strained Ge/Si1-yGey regions that are compatible with mid-gap work function metals and well-known high k/metal gate integration, while being self-aligned and defect-free.
Implementation Method 1
The method involves using preferential oxidation to convert a Si fin into a Ge/Si1-yGey fin or nanowire channel
Data Source
AI summary
A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an Si material and a Si1-xGex material; and exposing the first projection to preferential oxidation to yield a second projection including a center region comprising Ge/Si1-yGey and a covering region comprising SiO2 and enclosing the center region.