GeSn Gate-All-Around Channel Structure for Defect-Controlled Scaling
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Solution Overview
Problem
Germanium tin (GeSn) nanosheets/nanowires used in gate-all-around finFET devices face challenges such as dislocation defects, reduced dimensions, and decreased Ion/Ioff ratio due to scaling, necessitating improved etch selectivity and carrier mobility.
Innovation Solution
A GeSn GAA semiconductor device is formed with a buffer layer and stacked fin structure, including GeSn with a Sn concentration of 2-12% to enhance carrier mobility and etch selectivity, and S/D epitaxial structures doped with boron or phosphorus/arsenic, with a gate structure wrapping around to mitigate short-channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If GeSn nanosheets/nanowires are used in gate-all-around finFET devices, then carrier mobility is improved, but dislocation defects occur
Solution Approach 1:
A buffer layer is introduced as an intermediary between the substrate and the GeSn nanosheets/nanowires. This buffer layer acts as a mediator that accommodates lattice mismatch and reduces dislocation defects while allowing the GeSn channel to maintain its high carrier mobility properties.
Solution Approach 2:
The tin concentration in the GeSn alloy is optimized within a specific range (2-12% Sn) to balance the competing requirements: higher Sn content increases carrier mobility but also increases lattice mismatch and dislocation density. By controlling the Sn concentration parameter, the patent achieves improved mobility while limiting defect formation.
2Productivity
If device dimensions are scaled down, then storage capacity and processing speed are improved, but manufacturing complexity increases
Solution Approach 1:
The gate structure is designed to wrap around the channel in a gate-all-around configuration, with the gate electrode nested within the dielectric layer that surrounds the channel from all sides. This nested structure provides superior gate control at scaled dimensions while maintaining manufacturability through standard semiconductor processing techniques.
Solution Approach 2:
The device employs composite material structures including alternating layers of Ge and GeSn nanosheets/nanowires, combined with doped semiconductor layers and dielectric materials. This composite approach enables simultaneous optimization of carrier mobility, mechanical stability, and electrical isolation, addressing manufacturing challenges at scaled dimensions.
3Manufacturing precision
If Sn concentration is increased, then etch selectivity is improved, but dislocation defects increase
Solution Approach 1:
The tin concentration is precisely controlled within the 2-12% range to optimize etch selectivity between GeSn and other device materials. This parameter optimization ensures that the GeSn channel can be selectively etched or processed while maintaining acceptable dislocation density levels.
Solution Approach 2:
Different regions of the device may have different GeSn compositions optimized for their specific functions. The channel region uses GeSn with Sn concentration optimized for carrier mobility, while other regions may have different compositions optimized for etch selectivity or mechanical properties, allowing local optimization without compromising overall device reliability.
Data Source
AI summary
The present disclosure describes a semiconductor device includes a substrate, a buffer layer on the substrate, and a stacked fin structure on the buffer layer. The buffer layer can include germanium, and the stacked fin structure can include a semiconductor layer with germanium and tin. The semiconductor device further includes a gate structure wrapped around a portion of the semiconductor layer and an epitaxial structure on the buffer layer and in contact with the semiconductor layer. The epitaxial structure includes germanium and tin.