GeSn Stressed Source Drain Regions for CMOS Mobility
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Solution Overview
Problem
Traditional semiconductor technologies, such as those using Si1-xGex or Si1-xCx, impose limited strain on Si channels due to similar lattice constants, restricting carrier mobility and device drive capability, while GeSn alloy formation via molecular-beam epitaxy or CVD is not mature or compatible with CMOS processes, and high mobility materials like GaAs and InSb face integration challenges with Si-based CMOS.
Innovation Solution
A MOSFET with GeSn stressed source and drain regions is developed, where GeSn alloy is formed by precursor implantation and laser rapid annealing, with Sn concentration between 0 and 30%, enhancing carrier mobility and device drive capability, and the method includes pre-amorphization ion implantation and a protective layer to control Sn distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional materials like Si1-xGex or Si1-xCx are used for stressed source/drain regions, then the manufacturing process is compatible with CMOS, but the lattice constants are not sufficiently different from Si, providing limited strain and restricting carrier mobility enhancement
Solution Approach 1:
The patent changes the material composition parameter by using GeSn alloy with varying Sn concentrations (x values from 0 to 0.3) to achieve different lattice constants. This allows optimization of strain magnitude on the Si channel while maintaining CMOS process compatibility through precursor implantation and laser annealing
Solution Approach 2:
The patent employs GeSn alloy, a composite material combining Ge and Sn elements, to achieve lattice constant differentiation from Si. The composite nature of GeSn allows tuning of physical properties including lattice constant and carrier mobility, resolving the contradiction between manufacturability and strain effectiveness
2Manufacturing precision
If GeSn alloy is formed via molecular-beam epitaxy or CVD, then high Sn concentration can be achieved, but the process is not mature or compatible with CMOS currently
Solution Approach 1:
The patent replaces the complex epitaxial growth system (molecular-beam epitaxy or CVD) with a simpler ion implantation and laser annealing process. This substitution achieves comparable or superior Sn concentration control while ensuring CMOS process compatibility, as ion implantation and laser annealing are established CMOS fabrication techniques
Solution Approach 2:
The patent changes the manufacturing approach from epitaxial growth to ion implantation followed by laser annealing. This parameter change in the fabrication process enables precise Sn concentration control through implantation dose adjustment while maintaining compatibility with existing CMOS production lines
3Productivity
If device size is reduced to enhance integration and reduce power consumption, then threshold voltage is reduced, but device drive capability is limited by low carrier mobility in traditional silicon material
Solution Approach 1:
The patent changes the material parameter from traditional Si to GeSn alloy in the source/drain regions. This material parameter change induces strain in the Si channel, which enhances carrier mobility and compensates for the drive capability limitations imposed by device scaling, thereby resolving the contradiction between integration density and carrier mobility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach effectively enhances carrier mobility and device drive capability by forming GeSn stressed regions with high Sn concentration, improving compatibility with CMOS technology and overcoming limitations of traditional materials.
Implementation Method 1
performing a laser rapid annealing such that the precursors react to produce GeSn alloy
Implementation Method 2
performing a laser rapid annealing such that the precursors react to produce GeSn alloy
Implementation Method 3
implanting precursors in the substrate on at least one side of the gate stack structure
Data Source
AI summary
The present invention discloses a semiconductor device, comprising: a substrate, a gate stack structure on the substrate, source and drain regions in the substrate on both sides of the gate stack structure, and a channel region between the source and drain regions in the substrate, characterized in that at least one of the source and drain regions comprises a GeSn alloy. In accordance with the semiconductor device and method for manufacturing the same of the present invention, GeSn stressed source and drain regions with high concentration of Sn is formed by implanting precursors and performing a laser rapid annealing, thus the device carrier mobility of the channel region is effectively enhanced and the device drive capability is further improved.