GFCI Leakage Detection with Adaptive RMS Trip Timing
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Solution Overview
Problem
Existing GFCI products face issues with two-chip solutions that occupy PCB space, use more components, reduce reliability, and lack backup protection, leading to false trips and high manufacturing costs due to fixed delay mechanisms and inefficient RMS calculations.
Innovation Solution
An integrated circuit with sensing circuitry and control logic that intelligently monitors leakage current, performs adaptive RMS calculations, and selectively activates components to conserve power and reduce false trips, allowing programmable trip delays based on actual leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a two-chip solution is used for GFCI sensing and control, then the sensing functionality can be implemented, but PCB space is occupied, component count increases, reliability decreases, and manufacturing cost increases
Solution Approach 1:
The patent combines the sensing circuitry and control logic into a single integrated circuit device. This merging eliminates the need for separate two-chip solutions, reducing component count while improving reliability through fewer interconnections and a unified design architecture.
2Reliability
If fixed delay mechanisms are used in GFCI trip logic, then simple control is achieved, but false trips occur and manufacturing cost increases due to inefficiency
Solution Approach 1:
The patent implements dynamic trip delay adjustment based on the characteristics of the detected leakage current. The control logic analyzes the leakage current waveform and adaptively sets the trip delay period, allowing shorter delays for clear faults and longer delays for ambiguous cases, thereby reducing false trips while maintaining manufacturing efficiency through software-based control.
Solution Approach 2:
The patent changes the trip delay parameter dynamically based on leakage current characteristics. By monitoring the leakage current magnitude and waveform, the system adjusts the trip delay period to optimize between rapid response for genuine faults and delayed response for potential false trips, eliminating the need for fixed conservative delay settings.
3Measurement precision
If continuous RMS calculations are performed in GFCI monitoring, then accurate leakage detection is achieved, but power consumption increases and processing overhead increases
Solution Approach 1:
The patent implements periodic RMS calculations at strategically selected time points during the AC cycle rather than continuous computation. The control logic triggers RMS calculations only when leakage current exceeds certain thresholds or at specific phases of the AC waveform, maintaining detection accuracy while significantly reducing processing overhead and power consumption.
Solution Approach 2:
The patent performs preliminary filtering and threshold checking before initiating full RMS calculations. The control logic first detects gross leakage current excursions using simple threshold comparisons, and only when these are exceeded does it proceed to more computationally intensive RMS calculations, thereby reducing overall processing requirements while maintaining accurate detection capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces component count, enhances reliability, avoids nuisance trips, and enables cost-effective implementation in inexpensive microcontrollers while providing accurate RMS calculations and variable trip delays.
Implementation Method 1
The GFCI device may contain a current transformer or solid state switch with both the hot (or live) wire and the neutral wire passing through the same coil. When there is mismatch in amplitude and/or the phase angle is not 180 degrees between the hot and neutral wires, the current transformer or solid state switch becomes unbalanced due to a leakage of current to the ground, which the current transformer or solid state switch can detect.
Data Source
AI summary
An integrated circuit includes front-end circuitry coupled to a current sensor, which is coupled to alternating current (AC) mains, and to convert a leakage current to a converted voltage. An analog-to-digital converter (ADC), coupled to the front-end circuitry, converts the converted voltage to a digital signal. The ADC includes limit detection circuitry to detect the digital signal indicating the converted voltage is lower than a low threshold limit or higher than a high threshold limit and output a limit interrupt in response to the detection. Control logic is coupled to an output of the ADC and to process, in response to receiving the limit interrupt, the digital signal to determine a root mean square (RMS) value, and output a trip signal to trip logic to cause a disconnect of a current supplied to a load by the AC mains in response to the RMS value satisfying a threshold trip value.