GFET Distributed Amplifier Layout for Gain and Bandwidth
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Solution Overview
Problem
Graphene field-effect transistors, due to being gapless materials, face challenges in providing ideal gain for microwave amplifiers, limiting their high-frequency electronic device applications.
Innovation Solution
A distributed amplifier design incorporating a drain transmission line, a gate transmission line, and sequentially arranged graphene field-effect transistors with specific matching sections and shunt capacitors and inductors, synchronized to enhance amplification capabilities and bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single graphene field-effect transistor is used, then the device structure is simple, but the gain and bandwidth are insufficient
Solution Approach 1:
The amplifier is divided into multiple identical GFET stages connected in sequence, with each stage contributing to the overall gain. The gate transmission line and drain transmission line are segmented into multiple sections with matching sections at both ends, allowing the gain to be additive across stages while maintaining impedance control and reducing peaking effects.
2Power
If multiple graphene field-effect transistors are arranged in parallel, then the gain increases, but the bandwidth and performance improvement are limited
Solution Approach 1:
The gate transmission line and drain transmission line provide continuous signal paths across all GFET stages, with signals propagating continuously through the transmission lines. The matching sections ensure continuous impedance matching, preventing signal reflections and maintaining broadband operation, thus achieving both high gain and improved bandwidth.
3Reliability
If matching sections are added to the transmission lines, then the peaking effect is reduced and performance is improved, but the device complexity increases
Solution Approach 1:
Matching sections are strategically placed only at the input and output ends of the gate and drain transmission lines, where impedance matching is most critical. Each matching section consists of specific LC components configured to provide the necessary impedance transformation, improving performance without adding matching elements throughout the entire structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The distributed amplifier achieves improved performance and gain, with output voltage proportional to the number of graphene field-effect transistors, effectively addressing the limitations of single graphene transistors and enhancing bandwidth.
Implementation Method 1
a gate transmission line, in which the gate transmission line comprises a third matching section at a first end of the gate transmission line and a fourth matching section at a second end of the gate transmission line
Implementation Method 2
gates of the graphene field-effect transistors respectively connected with a plurality of first shunt capacitors which are grounded
Implementation Method 3
having a plurality of first inductors respectively between each two first nodes
Implementation Method 4
each of the first matching section, the second matching section, the third matching section and the fourth matching section includes a first capacitor, a third inductor and a fourth inductor; in which the first capacitor, the third inductor and the fourth inductor are connected in series
Data Source
AI summary
The present disclosure provides a distributed amplifier, including: a drain transmission line; a gate transmission line; GFETs, in which sources of the graphene field-effect transistors are respectively grounded; gates of the graphene field-effect transistors respectively connected with a plurality of first shunt capacitors which are grounded; the gate transmission line is connected with a plurality of first nodes respectively between the gates of the graphene field-effect transistors and the plurality of first shunt capacitors, having a plurality of first inductors respectively between each two first nodes; drains of the graphene field-effect transistors respectively connected with a plurality of second shunt capacitors which are grounded; the drain transmission line is connected with a plurality of second nodes respectively between the drains of the graphene field-effect transistors and the plurality of second shunt capacitors, having a plurality of second inductors respectively between each two second nodes.


