GGNMOS ESD Circuit With Ballast Trigger Equalization

Solution Overview

Problem

Existing ESD circuits with GGNMOS transistors face challenges in ensuring all transistors become conductive during an ESD event due to varying trigger rail path distances, leading to inconsistent voltage levels and potential damage to semiconductor devices.

Innovation Solution

Incorporating ballast circuits between the body contacts of GGNMOS transistors and the trigger rail to equalize voltage levels, ensuring all transistors conduct during an ESD event by providing differential headroom and equalizing resistances or forward voltage drops based on path distance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple GGNMOS transistors are used in parallel for ESD discharge, then the ESD discharge capability is improved, but the voltage level consistency across transistors deteriorates due to varying trigger rail path distances

Engineering Contradiction:

ImproveESD discharge capabilityVSAvoidvoltage level consistency

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies local quality by introducing ballast circuits with different resistance values at different locations. Specifically, ballast circuits closer to the trigger device have lower resistance values, while those farther away have higher resistance values. This localized variation in resistance compensates for the varying path distances, ensuring that each GGNMOS transistor receives an appropriate voltage level to become conductive during ESD events.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes the resistance parameter of ballast circuits based on their location relative to the trigger device. By adjusting the resistance values of ballast circuits according to their position, the patent equalizes the voltage levels at the body contacts of all GGNMOS transistors despite different path distances, thereby resolving the voltage consistency issue.

Inventive Principle:

Principle #35Parameter changes

2Manufacturing precision

If ballast circuits are added to equalize voltage levels, then the voltage consistency across transistors is improved, but the device complexity increases

Engineering Contradiction:

Improvevoltage level consistencyVSAvoidcircuit structure

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent segments the ESD circuit into multiple independent units, each consisting of a GGNMOS transistor with its associated ballast circuit. This segmentation allows each transistor-ballast pair to be designed and optimized independently, making the overall system more manageable despite the added complexity. The modular structure facilitates easier analysis, design, and potential manufacturing.

Inventive Principle:

Principle #1Segmentation

3Adaptability or versatility

If GGNMOS transistors are located at different distances from the trigger device, then the circuit layout flexibility is improved, but the trigger reliability deteriorates due to varying voltage levels

Engineering Contradiction:

Improvecircuit layout flexibilityVSAvoidtrigger reliability

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent applies local quality by introducing ballast circuits with different resistance values at different locations. Specifically, ballast circuits closer to the trigger device have lower resistance values, while those farther away have higher resistance values. This localized variation in resistance compensates for the varying path distances, ensuring that each GGNMOS transistor receives an appropriate voltage level to become conductive during ESD events.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS20250343408A1ESD circuit with ggnmos transistors and ballast circuits

Publication Date: 2025.11.06 NXP BV

AI summary

An electrostatic discharge circuit for a semiconductor die includes a plurality of GGNMOS transistors coupled between a first rail and a second rail of the semiconductor die. Each GGNMOS transistor includes a body contact that is coupled to a trigger rail through a ballast circuit and is coupled to the second rail. During the detection of an ESD event of a sufficient severity, the trigger rail is placed in an asserted condition to make the GGNMOS transistors conductive to discharge ESD current from the first rail to the second rail.