Parallel Pipelined Apparatus for GHASH Hash Function Computation
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Solution Overview
Problem
Current digital devices using the GHASH hash function suffer from low speed and limited configurability, restricting their ability to optimize performance and data processing efficiency.
Innovation Solution
A pipelined apparatus with multiple computation units and FIFO buffer registers is designed to parallelize the computation of the GHASH function, utilizing pipeline multipliers and feedback units to accelerate data processing and allow for flexible configuration based on specific application conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If sequential computation method is used, then device complexity is low, but computational speed is slow
Solution Approach 1:
The computation is divided into M parallel pipelines, each handling a portion of the data blocks. The apparatus segments the input data into M streams and processes them simultaneously through separate computation units, achieving M-fold speedup while maintaining manageable complexity through modular design
Solution Approach 2:
The invention transitions from sequential single-dimensional processing to parallel multi-dimensional processing by introducing M simultaneous computation paths. This dimensional expansion allows multiple operations to occur concurrently, dramatically increasing throughput without proportionally increasing critical path delay
2Adaptability or versatility
If fixed configuration is used, then manufacturing is simpler, but adaptability to different applications is limited
Solution Approach 1:
The apparatus incorporates configurable parameters M and L that can be adjusted based on application requirements. The system dynamically adapts its parallelism degree and pipeline depth to match specific performance needs, allowing optimization for different data block sizes and throughput requirements while maintaining a unified hardware architecture
Solution Approach 2:
The design creates a universal apparatus that can handle various GHASH computation scenarios by configuring the number of parallel units M and pipeline stages L. This multi-functional design covers a wide range of applications from low-speed to high-speed requirements without needing multiple specialized devices
3Productivity
If more data blocks are processed in parallel, then productivity increases, but device complexity increases
Solution Approach 1:
The apparatus nests multiple levels of parallelism: M parallel computation units are nested within a unified architecture that shares common resources such as the combining unit and control logic. This nested structure allows high productivity through parallel processing while containing complexity through resource sharing and hierarchical organization
Data Source
AI summary
The group of inventions relates to computing techniques and can be used for computing a hash function. The technical effect relates to increased speed of computations and improved capability of selecting a configuration of an apparatus. The apparatus comprises: a preliminary preparation unit having M inputs with a size of k bits, where M>1; M pipelined computation units running in parallel, each comprising: a memory module, a feedback disable module, an adder, a pipeline multiplier having L stages, a feedback unit, and an accumulation unit; and a combining unit.