Ghost Features for Gate Critical Dimension Variation Control
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Solution Overview
Problem
Current lithographic processes face challenges in controlling gate critical dimension variation, particularly at advanced technology nodes like 45 nm, where end gates are 2 to 3 times larger than interior gates, leading to interference and inefficient use of wafer real estate due to dummy gates.
Innovation Solution
The use of ghost features, which are initially formed adjacent to active features on the substrate and later removed, to improve critical dimension control by creating an environment similar to interior gates, thereby reducing size variations and minimizing interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dummy gates are used to compensate for end gate size variation, then gate critical dimension uniformity is improved, but wafer real estate is wasted and device density is reduced
Solution Approach 1:
The patent extracts and removes the dummy gates from the final device structure. Instead of keeping dummy gates as permanent structures, they are formed temporarily during lithography to provide optical assistance for end gate sizing, then completely removed in subsequent etching steps. This eliminates the waste of wafer real estate while preserving the benefit of improved critical dimension uniformity during the patterning process.
Solution Approach 2:
The patent applies preliminary action by forming dummy gates before the final device structure is completed. The dummy gates are created during the lithography process to provide optical assistance for accurate end gate sizing, then removed in subsequent processing steps. This preliminary formation allows the system to benefit from improved sizing accuracy without the long-term penalty of permanent dummy structures occupying wafer space.
2Reliability
If end gates are made larger to compensate for optical effects, then manufacturing yield is improved, but critical dimension variation increases and device density decreases
Solution Approach 1:
The patent applies local quality by providing different optical assistance to different regions of the gate array. Interior gates receive standard optical treatment, while end gates receive enhanced optical assistance through the addition of dummy gates specifically positioned adjacent to end gates. This localized modification compensates for the specific optical effects affecting end gates without altering the entire gate array, thereby improving critical dimension uniformity while maintaining device density.
Solution Approach 2:
The patent uses copying by creating dummy gates that are identical copies of the active gates. These dummy gates are formed using the same lithography process and have the same dimensions and material properties as the active gates. The dummy gates serve as optical references for end gate sizing, allowing the end gates to be accurately sized without requiring them to be physically larger, thus reducing critical dimension variation while maintaining manufacturing yield.
3Ease of manufacture
If dummy gates are retained in the final device, then processing simplicity is maintained, but interference between gates increases and device performance deteriorates
Solution Approach 1:
The patent extracts and removes dummy gates from the final device structure through selective etching. After the dummy gates serve their optical assistance function during lithography, they are completely removed in subsequent etching steps. This eliminates the harmful interference between dummy gates and active gates while preserving the benefit of improved end gate sizing that occurred during the patterning process.
Solution Approach 2:
The patent discards the dummy gates after they have served their temporary purpose. The dummy gates are formed during lithography to provide optical assistance, then completely removed in subsequent processing steps. This discarding approach eliminates the harmful interference that would occur if dummy gates were retained, while the optical benefit is recovered during the critical patterning process before removal.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Ghost features allow for accurate sizing and spacing of active gates, reducing critical dimension variation by up to 10% and eliminating unnecessary processing steps, thus improving the fidelity of gate arrays and optimizing wafer usage.
Implementation Method 1
a projection system of the tool... each target portion is irradiated by exposing the entire mask onto the target portion
Implementation Method 2
radiation-sensitive material, such as a resist... After exposure, the substrate can be subjected to other procedures
Data Source
AI summary
According to various embodiments, the present teachings include various methods for forming a semiconductor device, computer readable medium for forming a semiconductor device, mask sets for forming a semiconductor device, and a semiconductor device made according to various methods. For example, a method can comprise forming a first feature and a second feature on a substrate by exposing a first mask to a first beam, wherein the second feature is disposed adjacent to the first feature, exposing a second mask to a second beam, and removing the second feature from the substrate.