GIDL Current Generation in Semiconductor Devices

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Solution Overview

Problem

Existing semiconductor devices face challenges in increasing the efficiency of gate-induced drain leakage (GIDL) current without deteriorating the insulating material between the GIDL line and the vertical channel layer, which is crucial for improving memory device integration density and reducing manufacturing costs.

Innovation Solution

A semiconductor device design that includes a source layer, channel structures with vertical insulating and channel layers, gate electrodes acting as GIDL lines, and a common source line with a memory controller that applies an erasing voltage with a targeted step-up and step-down mechanism to enhance GIDL current generation without damaging the insulating material.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the erasing voltage is increased to enhance GIDL current generation efficiency, then the GIDL current efficiency is improved, but the insulating material between the GIDL line and vertical channel layer deteriorates

Engineering Contradiction:

ImproveGIDL current generation efficiencyVSAvoidinsulating material integrity

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent applies dynamic voltage control by implementing a step-up voltage sequence during erasing operations. The controller increases the erasing voltage from an initial level to a higher level in steps, allowing the system to adapt to different operational phases. This dynamic approach enables efficient GIDL current generation at higher voltages while protecting the insulating material during voltage transitions, resolving the contradiction between productivity and reliability.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent implements periodic voltage application with specific step-up time periods. The controller applies erasing voltage in controlled intervals, increasing it to a step-up voltage for a designated time period, then reducing it back to the target voltage. This periodic action pattern allows sufficient time for GIDL current generation while preventing prolonged exposure to high voltages that would damage the insulating material, thus balancing efficiency improvement with material protection.

Inventive Principle:

Principle #19Periodic action

2Speed

If the erasing voltage is increased to reach target voltage faster, then the erasing operation speed is improved, but the insulating material between GIDL line and vertical channel layer is damaged

Engineering Contradiction:

Improveerasing operation speedVSAvoidinsulating material damage

Core Design Contradiction:

SpeedVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary protective actions by establishing a controlled voltage increase protocol before reaching target voltage. The controller implements step-up voltage sequences with predetermined time periods, preparing the system for efficient erasing while pre-establishing protection mechanisms. This preliminary structured approach ensures fast erasing speed is achieved without subjecting the insulating material to sudden voltage shocks that would cause damage.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements beforehand cushioning by introducing intermediate voltage steps between the initial and target voltages. Rather than applying the full target voltage immediately, the controller increases voltage in controlled increments with specific time periods, cushioning the transition to protect the insulating material. This gradual voltage buildup maintains erasing speed while preventing material damage through buffered voltage application.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed solution effectively increases the efficiency of GIDL current generation while maintaining the integrity of the insulating material, thereby improving memory device integration density and reducing manufacturing costs.

Implementation Method 1

at least one gate electrode of the plurality of gate electrodes is configured to provide a gate-induced drain leakage (GIDL) line

Methodology Applied

Scientific EffectGate-induced drain leakage (GIDL): Avalanche Breakdown

Data Source

PatentUS11114165B2Semiconductor devices having increased efficiency in generation of gate-induced drain leakage current without insulation deterioration and methods of operating the same

Publication Date: 2021.09.07 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor device includes a source layer; a plurality of channel structures; a plurality of gate electrodes; and a common source line. At least one of the plurality of gate electrodes provides a GIDL line. For an erasing operation, an erasing voltage applied to the common source line reaches a target voltage, and, after the erasing voltage reaches the target voltage, a step increment voltage is applied to the erasing voltage, such that the erasing voltage has a voltage level higher than a voltage level of the target voltage. After the step increment voltage has been applied for a desired time period, the voltage level of the erasing voltage is decreased to the target voltage level for the remainder of the erasing operation.