GIDL Erase Voltage Stability via Gate Precharging
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Solution Overview
Problem
Current three-dimensional nonvolatile memory devices require high-level voltage for gate-induced drain leakage (GIDL) erase schemes, which can lead to inefficiencies and instability in the erase operation due to significant voltage drops across transistors during the erase process.
Innovation Solution
A memory device design that bypasses the transistor provided with the erase voltage by precharging the gate line and electrically floating it, allowing the erase voltage to be stepped up and applied directly to the bitline or common source line, thereby minimizing voltage loss and ensuring stable GIDL erase operations across various structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-level voltage is applied to perform GIDL erase operation through a transistor, then the erase operation can be achieved, but significant voltage drops occur across the transistor leading to instability and inefficiency
Solution Approach 1:
The gate line is precharged to a high voltage level before the erase operation begins. This preliminary action ensures that when the erase voltage is subsequently applied to the bitline or common source line, the transistor does not cause significant voltage drops because the gate is already at the required potential, thereby eliminating the need to overcome threshold voltage barriers during the actual erase process
Solution Approach 2:
The patent extracts the transistor from the voltage transmission path by electrically floating its gate during the erase operation. This is achieved by disconnecting the gate line from its normal control circuitry and maintaining it at a fixed high voltage level, thereby removing the transistor's active control function while preserving its passive conduction path for the erase voltage
2Productivity
If erase voltage is provided through a transistor to enable GIDL erase, then the erase function is achieved, but the operation becomes inefficient due to voltage loss
Solution Approach 1:
The gate line is precharged to a high voltage level before the erase operation begins. This preliminary action ensures that when the erase voltage is subsequently applied to the bitline or common source line, the transistor does not cause significant voltage drops because the gate is already at the required potential, thereby eliminating the need to overcome threshold voltage barriers during the actual erase process
Solution Approach 2:
The patent changes the voltage parameter of the gate line from a normally controlled variable voltage to a fixed high voltage level during the erase operation. By setting the gate voltage to a sufficiently high level and maintaining it there, the transistor operates in a regime where it acts as a low-resistance conduit rather than an active switch, minimizing voltage drops and maximizing erase efficiency
Data Source
AI summary
A memory device includes a memory cell array having a plurality of memory blocks therein, including a target memory block. A voltage generator is provided, which is configured to generate an erase voltage and row line voltages, which are provided to the target memory block upon which an erase operation is to be performed. Control logic is provided, which is configured to control the memory cell array and the voltage generator. In addition, during operation, the erase voltage is provided to at least one of a bitline or a common source line associated with the target memory block, and a gate line of a transistor provided with the erase voltage is precharged before the erase voltage is provided to the at least one of the bitline or the common source line of the target memory block.