Transparent Gigabit Ethernet Aggregation via Idle Character Stuffing
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Solution Overview
Problem
Existing technologies face challenges in transparently multiplexing packet-based data streams with different clock domains over high-speed optical networks, leading to issues with data transparency and buffer overflow due to clock mismatches and the need for costly ASICs.
Innovation Solution
The method involves aggregating multiple Gigabit Ethernet and Fibre Channel data streams onto a 10 Gbps optical transport link using an independent clock source, with Idle character stuffing to maintain transparency, and incorporating Forward Error Correction (FEC) for error correction, allowing data to be transmitted in its native format without encoding or protocol conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple Gigabit Ethernet and Fibre Channel data streams with different clock domains are multiplexed over a high-speed optical link, then data transmission capacity is improved, but data transparency is lost and buffer overflow occurs due to clock mismatches
Solution Approach 1:
The patent introduces an intermediary mechanism (idle character stuffing and timing recovery circuits) between the multiplexer and the optical link to handle clock domain mismatches. The idle characters act as a buffer that absorbs timing differences between input streams with different clock domains and the output link, maintaining data transparency while enabling high-capacity multiplexing.
Solution Approach 2:
The patent dynamically adjusts the timing parameters of data streams by inserting or removing idle characters based on the relative clock rates of input streams and the output link. This parameter change approach allows the system to adapt to different clock domain combinations while maintaining synchronous operation over the optical link.
2Ease of operation
If traditional SCSI architecture is used for storage connectivity, then device access is simplified, but scalability is limited due to finite device support and distance constraints
Solution Approach 1:
The patent merges multiple high-speed data streams (Gigabit Ethernet and Fibre Channel) onto a single optical link, combining the advantages of both protocols. This merging approach enables scalable storage networking while maintaining the simplicity of direct device access through protocol-agnostic transparent transport.
Solution Approach 2:
The patent creates a universal transport mechanism that can carry multiple protocol types (Gigabit Ethernet, Fibre Channel, and other packet-based formats) over a single optical link. This multi-functional approach eliminates the need for separate dedicated links for each protocol, enabling scalable storage networks with simplified device access.
3Ease of manufacture
If Gigabit Ethernet data streams are multiplexed without protocol conversion, then cost is reduced, but clock synchronization becomes difficult leading to transparency issues
Solution Approach 1:
The patent implements a self-service timing recovery mechanism that automatically detects and compensates for clock domain mismatches without requiring external synchronization infrastructure. The timing recovery circuits continuously monitor the relative timing of input streams and dynamically adjust idle character insertion rates, enabling cost-effective implementation without complex external clock synchronization.
4Reliability
If Forward Error Correction is integrated into the multiplexing apparatus, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the Forward Error Correction functionality with the existing multiplexing and timing recovery circuits, combining multiple functions into a single integrated apparatus. This merging approach improves reliability through error correction while minimizing the increase in device complexity by sharing hardware resources across multiple functions.
Data Source
AI summary
The invention provides an apparatus and method for transparently transporting four plesiochronous Gigabit Ethernet, Fibre Channel or other packet-based data signals over a network. Multiple plesiochronous Gigabit Ethernet data streams are aggregated onto an independent clock source at an ingress circuit through the use of transparent IDLE character insertion. The independent clock is selected such that the output data rate is greater than the composite input data rate of all the plesiochronous data streams. The signals are encapsulated with forward error correction and mapped to a reciprocal FEC interface prior to transport. An egress circuit at the receiving end recovers the modulated signal and extracts the data stream. Each independent data stream is mapped to a local clock domain via IDLE character insertion or removal. Therefore, the input and output signals are transparent and identical in content.