Gigabit Router Offloading NAT to Ethernet Switch

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Solution Overview

Problem

The high cost and latency associated with using System-on-Chip (SoC) multi-core processors in gigabit routers, which are necessary for high bitrates but increase manufacturing costs and reduce performance due to the requirement for each data packet to flow through the processor.

Innovation Solution

Implementing a gigabit router that does not use an SoC processor, instead leveraging auxiliary processors on a Wi-Fi module and a multi-port Ethernet switch to handle routing activities, with firmware executing on the Wi-Fi module to offload network address translation and packet forwarding onto hardware accelerators.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If an SoC multi-core processor is used to handle high bitrate routing operations, then the router can achieve gigabit data transfer rates, but the manufacturing cost increases significantly

Engineering Contradiction:
Improvedata transfer rateVSAvoidmanufacturing cost
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The patent divides the routing functionality into separate components: the Ethernet switch handles packet forwarding and network address translation independently from the Wi-Fi module's auxiliary processor. This segmentation allows each component to be optimized for its specific function, reducing the need for an expensive SoC processor while maintaining gigabit performance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent extracts the packet forwarding and NAT functions from the central SoC processor and implements them directly in the Ethernet switch hardware. This extraction eliminates the bottleneck of processor-based packet processing and reduces manufacturing costs by removing the requirement for high-performance processor components.

Inventive Principle:
Principle #2Taking out (Extraction)

2Productivity

If an SoC multi-core processor is used for routing operations, then high bitrate performance can be achieved, but latency increases due to processor processing requirements

Engineering Contradiction:
Improvedata transfer rateVSAvoidlatency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent replaces the software-based processor packet processing mechanism with hardware-based packet forwarding in the Ethernet switch. This substitution eliminates the sequential processing steps required by the SoC processor, enabling parallel packet forwarding and significantly reducing latency while maintaining high data transfer rates.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The Ethernet switch performs packet forwarding and network address translation actions in advance based on pre-configured hardware tables, eliminating the need for real-time processor intervention. This preliminary action approach allows packets to be forwarded immediately without waiting for processor processing, reducing latency.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If an SoC processor is used to manage routing functionalities, then comprehensive routing features can be implemented, but the number of required connection pins increases

Engineering Contradiction:
Improverouting functionalityVSAvoidconnection pins
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the routing functionalities across separate components: the Ethernet switch handles packet forwarding and NAT with its own dedicated pins, while the Wi-Fi module's auxiliary processor handles wireless-specific routing. This segmentation reduces the pin count requirements compared to a monolithic SoC that would need to accommodate all interfaces and functions on a single chip.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10412004B2Gigabit router
Publication Date: 2019.09.10 GOOGLE LLC
  • US10412004B2 patent drawing
  • US10412004B2 patent drawing
  • US10412004B2 patent drawing

AI summary

A method includes receiving a data packet over one of a wireless communication link or a wired communication link from a user device in the local network. The data packet includes internet protocol (IP) address information. The method also includes determining whether the IP address information includes corresponding packet forwarding rules. When the IP address information includes corresponding packet forwarding rules, the method includes performing network address translation on the IP address information by mapping a source IP address from a private source IP address subnet to a public source IP address subnet, attaching the public source IP address subnet to the header of the data packet, and forwarding the data packet from the Ethernet switch to an external network port. The external network port is configured to connect the network routing device to the external network.