Symmetrical Gilbert Mixer Layout for LO Leakage Reduction
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Solution Overview
Problem
Gilbert mixers suffer from frequency-dependent local oscillator (LO) leakage due to asymmetry in the circuit layout, which degrades radar sensitivity in Doppler Division Multiplexing (DDM) radar systems and limits error vector magnitude (EVM) in communication systems.
Innovation Solution
A symmetrical Gilbert mixer layout is achieved by aligning multi-finger field effect transistor (FET) devices orthogonally, connecting gate and source terminals symmetrically, and overlapping gate interconnects to minimize unequal trace lengths and reduce LO leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional Gilbert mixer layout is used, then the circuit is simple to implement, but LO leakage occurs due to asymmetry in the circuit layout
Solution Approach 1:
The patent applies asymmetry principle by intentionally introducing asymmetrical compensation elements (dummy traces, unequal length interconnects) to counterbalance the inherent asymmetries in the Gilbert mixer circuit. This involves adding compensatory trace length differences that match the asymmetries in transistor gate lengths, thereby canceling out the phase errors that cause LO leakage.
Solution Approach 2:
The patent implements counterweight by adding dummy transmission line traces that act as compensatory elements. These dummy traces are designed with specific length differences to counterbalance the phase errors introduced by unequal gate lengths of the FET devices, effectively weighing out the asymmetries in the circuit layout.
2Reliability
If unequal trace lengths are present in the circuit layout, then the circuit layout is simpler, but phase errors of multiple degrees occur introducing LO leakage
Solution Approach 1:
The patent applies local quality principle by making specific local modifications to the circuit layout, such as adding dummy traces only in specific locations where phase error compensation is needed. The compensation is applied locally at critical points in the circuit rather than requiring uniform precision throughout the entire layout.
Solution Approach 2:
The patent changes the trace length parameter intentionally to compensate for phase errors. By adjusting the length of dummy traces to match specific phase error values, the overall phase balance is improved despite variations in other trace lengths, transforming a precision problem into a parameter optimization problem.
3Reliability
If FET devices are arranged in a conventional layout, then the device area is smaller, but frequency dependent LO leakage degrades radar sensitivity
Solution Approach 1:
The patent addresses the area issue by optimizing the spatial arrangement of FET devices and interconnects in the planar layout. By carefully positioning devices and routing traces to minimize unequal path lengths while maintaining compactness, the design achieves good phase balance without excessive area expansion.
Data Source
AI summary
The disclosure relates to a Gilbert mixer. Example embodiments include a Gilbert mixer that includes first and second multi-finger field effect transistor, FET, devices, each including gate fingers arranged between alternating source terminals and drain terminals; first and second pairs of voltage rails arranged across the first and second FET devices respectively, each of the first and second pairs including an upper rail and a lower rail; a first interconnect connecting the upper rail of the first pair and the lower rail of the second pair to a first input terminal; and a second interconnect connecting the lower rail of the first pair and the upper rail of the second pair to a second input terminal. Gate fingers of the first FET device are connected to the first pair of voltage rails and gate fingers of the second FET device are connected to the second pair of voltage rails.