Dynamic Clock Frequency Control for GIP Circuitry Power Reduction

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Solution Overview

Problem

Electronic displays consume significant power even during low refresh rates due to unaltered clock frequencies in control circuitry, such as gate-in-panel (GIP) circuitry, despite reduced display activity, leading to inefficient power management.

Innovation Solution

Implementing a method to reduce or halt clock signal frequencies to the GIP circuitry during extended blanking operations, allowing for dynamic frequency adjustments based on display mode, thereby reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the display refresh rate is reduced to lower power consumption, then energy efficiency is improved, but clock frequency in control circuitry remains unchanged causing continued high power draw

Engineering Contradiction:

Improvepower consumptionVSAvoidcontrol circuitry operation

Core Design Contradiction:

Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent applies dynamics by making the clock frequency adjustable rather than fixed. The system dynamically changes the clock frequency sent to GIP circuitry based on the display refresh rate - using full frequency during normal operation and reduced frequency during extended blanking periods. This dynamic adaptation resolves the contradiction by allowing power consumption to be reduced without compromising control circuitry functionality when needed.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the clock frequency parameter in response to display mode changes. When the display enters extended blanking mode with lower refresh rates, the system changes the clock frequency parameter from full speed to a reduced frequency, directly addressing the power consumption issue while maintaining circuitry operational capability.

Inventive Principle:

Principle #35Parameter changes

2Use of energy by moving object

If clock frequency is reduced during low refresh rates, then power consumption in control circuitry is reduced, but display performance may be compromised

Engineering Contradiction:

Improvepower consumption in control circuitryVSAvoiddisplay performance

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The system dynamically adjusts clock frequency based on display mode, ensuring full frequency is restored when high performance is needed and reduced frequency is applied when power saving is the priority. This dynamic switching resolves the contradiction by contextually adapting the clock frequency to match actual display performance requirements.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent implements periodic switching between full clock frequency and reduced clock frequency based on display refresh cycles. During extended blanking periods, reduced frequency is applied to save power, while during active display periods, full frequency is restored to ensure performance. This periodic action resolves the contradiction by alternating between power-saving and performance modes appropriately.

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS12062313B2Systems and methods for clock frequency control during low display refresh rates in electronic devices

Publication Date: 2024.08.13 APPLE INC

AI summary

This disclosure is directed towards systems and methods of power saving in electronic displays based on changing clock signal frequencies supplied to the gate-in-panel (GIP) circuitry during extended blanking modes of the electronic display. The display driver circuitry of the display may reduce and/or halt clock signal frequencies sent to GIP circuitry in the display, to reduce power output during extended blanking modes of the electronic display.