GIP Display Panel Clock Line Layout for Narrow Bezels
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Solution Overview
Problem
Existing display technologies face challenges in achieving a narrow bezel design due to output deviations between shift clock lines in the bezel area of display panels.
Innovation Solution
The proposed solution involves a display panel design where the clock line area is disposed closest to the active area, with ground, gate-in-panel circuit, and low-voltage line areas sequentially arranged in the bezel area, and all shift clock signal lines overlapping the cathode, forming a double metal structure with the ground and low-voltage supply lines on the same layer as the first metal pattern.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the clock line area is disposed away from the active area in the bezel area, then there is sufficient space for routing clock lines, but the bezel width increases and cannot achieve narrow bezel design
Solution Approach 1:
The patent applies dimensionality change by arranging the clock line area in the vertical direction closest to the active area, utilizing the vertical space in the bezel area. This spatial reorganization allows the clock lines to be positioned optimally without increasing horizontal bezel width, thereby achieving narrow bezel design while maintaining proper clock line routing and minimizing output deviation.
Solution Approach 2:
The patent applies local quality by specifically positioning the clock line area with particular properties (closest to active area) different from other line areas (data line area farthest, gate line area intermediate). This differentiated spatial arrangement optimizes each line type's position according to its specific requirements, enabling narrow bezel while preventing clock line output deviation.
2Length of moving object
If multiple line areas are arranged in the bezel area, then all necessary connections are provided, but spatial conflicts arise making narrow bezel difficult to achieve
Solution Approach 1:
The patent applies segmentation by dividing the bezel area into distinct line areas (clock line area, data line area, gate line area) with clear spatial separation. Each segment is assigned a specific function and position, eliminating spatial conflicts while maintaining all necessary connections. This segmented arrangement enables narrow bezel design by optimizing the compact placement of each line area.
3Reliability
If the clock lines do not overlap the cathode, then there is less parasitic capacitance, but output deviation occurs between clock lines
Solution Approach 1:
The patent applies equipotentiality by ensuring all clock lines overlap the cathode in the same manner, creating uniform electrical conditions for each clock line. This consistent overlapping arrangement equalizes the parasitic capacitance experienced by each clock line, thereby eliminating output deviation between clock lines while maintaining controlled parasitic capacitance levels.
Data Source
AI summary
A gate-in-panel (GIP) display panel and a device are discussed, which are capable of resolving an output deviation between shift clock lines disposed in a bezel area and easily achieving a narrow bezel. The display panel can include an active area configured to display an image, and a bezel area disposed around the active area. Further, a ground area, a clock line area, a GIP circuit area, and a low-voltage line area can be disposed in the bezel area, and the clock line area can be disposed closest to the active area.