GIP Gate Driver Node Sharing for Reduced TFT Count
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Solution Overview
Problem
The existing gate drivers for flat panel display devices, particularly LCDs, require a large number of thin-film transistors, leading to increased bezel size and reduced aesthetic design, as well as limitations in panel fabrication due to the extensive inactive areas needed for the gate-in-panel (GIP) structure.
Innovation Solution
The proposed solution involves a GIP type gate driver that reduces the number of thin-film transistors by sharing Q and QB nodes among channels, using fewer transistors per channel, and incorporating compensation or discharge units to minimize output voltage deviations, thereby reducing the size of the gate driver and improving output characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional GIP gate driver is used with separate Q nodes for each channel, then each channel can operate independently, but the number of thin-film transistors increases and the gate driver size increases
Solution Approach 1:
The patent merges Q nodes by making them shared between adjacent channels (e.g., Q1 node shared by channel 1 and 2, Q2 node shared by channel 3 and 4). This combining of previously separate components reduces the total number of thin-film transistors while maintaining proper channel operation through coordinated control signals.
2Device complexity
If the number of thin-film transistors is reduced in the gate driver, then the gate driver size decreases and bezel size is reduced, but the output voltage stability may deteriorate
Solution Approach 1:
The patent incorporates compensation units that include feedback mechanisms to detect and correct output voltage deviations. The compensation units adjust the output voltage based on detected deviations, ensuring stable operation despite the reduced number of transistors and shared Q nodes.
Solution Approach 2:
The patent changes operating parameters by introducing compensation signals and adjusting transistor gate voltages dynamically. The compensation units modify voltage levels and timing parameters to maintain output stability under the new reduced-transistor configuration.
3Device complexity
If Q nodes are shared among channels, then the number of thin-film transistors is reduced by 40%, but output voltage deviations between channels may increase
Solution Approach 1:
The compensation units implement feedback control to detect output voltage deviations between channels and generate corrective signals. This feedback mechanism ensures that voltage consistency is maintained across all channels despite sharing Q nodes.
Solution Approach 2:
The patent applies local compensation to each channel or channel pair by introducing individual compensation units with discharge transistors. Each compensation unit is tailored to correct specific deviations in its associated channels, providing localized precision control.
Data Source
AI summary
In a gate driver, a Q node is shared by two channels to output a scan signal at high level, and a QB node is shared by four channels to output a scan signal at low level. Accordingly, the number of thin-film transistors required to configure four channels of a gate-in-panel (GIP) is reduced, such that the bezel size can be reduced. Further, the gate driver includes a compensation capacitor or a discharge transistor disposed in some of the channels sharing the Q node, such that deviation in output characteristics among the channels sharing the Q node can be reduced.