Thin Film Transistor Array Substrate GIP Jumper Reliability
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Solution Overview
Problem
The reliability of Gate driver In Panel (GIP) in thin film transistor array substrates is compromised due to disconnection of jumpers caused by height differences and over-etching during the manufacturing process, leading to potential short-circuits and reduced performance.
Innovation Solution
A thin film transistor array substrate design that includes a Gate driver In Panel (GIP) with a third insulating film having distinct thickness areas, where the area corresponding to the gap between contact holes is thicker to prevent disconnection and minimize height differences, and a manufacturing method that uses a half-tone mask to pattern the photoresist film, ensuring reliable jumper connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the first and second contact holes are formed via the same exposure masking process, then the number of masking processes is minimized, but over-etching of the second insulating film occurs causing height difference increase and jumper disconnection
Solution Approach 1:
The patent divides the formation of first and second contact holes into separate masking processes. The first contact hole is formed in the first insulating film using a first exposure mask, and the second contact hole is formed in the second insulating film using a second exposure mask. This segmentation prevents over-etching by controlling each etching process independently, thereby improving manufacturing precision while maintaining productivity.
Solution Approach 2:
The patent forms the first contact hole and removes the first exposure mask before forming the second contact hole. This preliminary action ensures that the first insulating film is properly prepared and the first contact hole is fully formed before proceeding to the second contact hole, preventing etching interference and height difference issues.
2Ease of manufacture
If the exposure mask is removed after formation of both contact holes, then the process is simplified, but the second insulating film tapered portion is partially removed causing increased height difference
Solution Approach 1:
The patent segments the mask removal process into two separate steps: removing the first exposure mask after forming the first contact hole, and removing the second exposure mask after forming the second contact hole. This prevents simultaneous removal that would cause the tapered portion damage, while maintaining ease of manufacture through a systematic approach.
Solution Approach 2:
The patent removes the first exposure mask before forming the second contact hole, cushioning against the potential damage to the second insulating film tapered portion. This prior action prevents the harmful effect of mask removal on the fragile tapered structure before it can occur.
3Device complexity
If the third insulating film has uniform thickness, then the manufacturing process is simplified, but height difference in the gap region causes jumper disconnection
Solution Approach 1:
The patent applies local quality by forming the third insulating film with different thicknesses in different regions. The film thickness in the gap region between contact holes is specifically controlled to be greater than in other regions, providing local compensation for height differences and preventing jumper disconnection while maintaining overall structural simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the reliability of the jumper connections and the overall GIP by preventing disconnection and reducing parasitic capacitance, thereby improving the stability and performance of the thin film transistor array substrate.
Implementation Method 1
a manufacturing method that uses a half-tone mask to pattern the photoresist film
Data Source
AI summary
Disclosed is a thin-film transistor array substrate including a Gate driver In Panel (GIP). The GIP includes a first wiring on a substrate, a first insulating film covering the first wiring, a second wiring on the first insulating film, a second insulating film covering the second wiring, a third insulating film over the second insulating film, first and second contact holes to expose the first and second wirings, and a third wiring on the third insulating film for connection of the first and second wirings. The third insulating film includes a first area corresponding to the first and second contact holes, a second area corresponding to a region between the first and second contact holes within a first thickness range, and a remaining third area within a second thickness range, the minimum value of the first thickness range being greater than the maximum value of the second thickness range.