GIP LCD Clock Phase Alternation for Vertical Muras
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Solution Overview
Problem
The combination of Dual-Gate and Gate-In-Panel (GIP) technologies in liquid crystal display devices can lead to undercharging of thin film transistors (TFTs), resulting in vertical muras and poor display quality.
Innovation Solution
A GIP type liquid crystal display device is designed with a clock generating unit that provides K scan clock signals to separate gate driving subunits, implementing alternating scan sequences to ensure consistent luminance across odd and even numbered pixel units, thereby reducing vertical muras and improving display effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If both GIP technology and dual-gate technology are employed to reduce costs, then the quantity of gate driving ICs is reduced and total costs are reduced, but vertical muras occur due to undercharge of TFTs
Solution Approach 1:
The gate lines are divided into odd-numbered groups and even-numbered groups, with separate driving circuits (first driving circuit and second driving circuit) controlling each group. This segmentation allows independent control of scanning sequences for different gate line groups, enabling the system to maintain cost benefits of GIP technology while avoiding vertical muras through differential scanning control.
Solution Approach 2:
The patent implements dynamic scanning sequence control where the first driving circuit and second driving circuit can operate with different scanning sequences. By dynamically adjusting which group scans first (odd or even) based on frame timing, the system compensates for charging differences and eliminates vertical muras while maintaining the integrated gate driving architecture.
2Device complexity
If gate lines are scanned in fixed sequence, then driving control is simplified, but luminance inconsistency occurs between odd and even numbered pixel units
Solution Approach 1:
The system dynamically switches scanning sequences between frames. In odd-numbered frames, the first driving circuit scans odd-numbered gate lines first; in even-numbered frames, the second driving circuit scans even-numbered gate lines first. This dynamic adjustment compensates for charging differences without requiring complex per-pixel control, maintaining relatively simple driving control while achieving luminance consistency.
Solution Approach 2:
The patent implements periodic alternation of scanning sequences between odd and even frames. This periodic action creates a time-averaged compensation effect where each pixel unit receives appropriate charging over successive frames, eliminating luminance inconsistency while maintaining a regular, predictable driving pattern that does not significantly increase control complexity.
Data Source
AI summary
A GIP liquid type of crystal display device includes a clock generating unit that provides K scan clock signals to a first driving subunit and K scan clock signals to a second driving subunit respectively according to a scan sequence to make the first/second driving subunit provides driving signals to odd/even numbered rows of gate lines. In a first scan sequence, the time sequence of the scan clock signals to scan the (2N)th row of gate line lags behind that of the scan clock signals to scan the (2N−1)th row of gate line by ½K of a cycle, while in a second scan sequence, the time sequence of the scan clock signals to scan the (2N−1)th row of gate line lags behind that of the scan clock signals to scan the (2N)th row of gate line by ½K of a cycle, wherein N is a natural number, K=2m, and m is a natural number.