GIP Shift Register Reset Signal Timing for Display Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In organic light emitting display devices with a gate-in-panel (GIP) type, the initial operation of the shift register often results in abnormal operations due to inadequate reset of the Q node, leading to potential short circuits and unstable driving characteristics, especially in panels with plastic substrates or increasing size and resolution.
Innovation Solution
A display device and method where a timing controller generates and continuously supplies a reset signal overlapping with clocks to the shift register during the initial frame, ensuring proper reset and preventing short circuits by maintaining the start signal in a turn-off state and avoiding overlap of reset and clock pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the reset signal QRST and the fourth clock CLK4 are simultaneously input to the stage, then the shift register is reset, but the Q node cannot be normally reset due to greater load of the reset signal, causing short circuit and abnormal operation
Solution Approach 1:
The patent applies preliminary action by continuously supplying the reset signal to the shift register before and during the initial clock operations. The reset signal is supplied in advance and maintained throughout the first frame, ensuring the Q node is properly initialized before any clock signals are applied, thus preventing the short circuit issue that occurs when reset and clock signals are simultaneously applied without proper timing control.
2Speed
If the pull-down transistor T6 is turned on prior to the reset transistor Tqrst, then the fourth clock CLK4 can be output, but the Q node and QB node are not simultaneously reset, causing output short circuit
Solution Approach 1:
The patent ensures simultaneous reset by maintaining the reset signal continuously active before clock signals are applied. The reset signal is supplied in advance and overlaps with the initial clock operations, ensuring both Q node and QB node are reset simultaneously before any clock output occurs, preventing the short circuit while maintaining proper operation speed.
Solution Approach 2:
The patent applies beforehand cushioning by continuously maintaining the reset signal active during the initial frame operations. This continuous reset signal acts as a protective measure that prevents the Q node and QB node from being in unknown states, cushioning against the potential short circuit that would occur if the reset timing were not properly controlled relative to the clock signals.
3Area of stationary object
If the reset transistor Tqrst is smaller in size than the pull-down transistor T6, then the device area is reduced, but the load on the reset signal increases, causing delayed turn-on and short circuit
Solution Approach 1:
The patent applies preliminary action by continuously supplying the reset signal before and during the initial clock operations. This continuous reset signal ensures that even though the reset transistor is small and has greater load, the Q node is properly initialized before any clock signals are applied, preventing the short circuit issue that would occur with delayed reset transistor turn-on.
Solution Approach 2:
The patent applies continuity of useful action by maintaining the reset signal continuously active throughout the first frame rather than applying it as a single pulse. This continuous reset signal ensures that the Q node remains properly initialized throughout the initial operations, compensating for the delayed turn-on caused by the small reset transistor size and high load.
Data Source
AI summary
Discussed are a display device and a method of driving the same. The display device can include a panel in which a pixel is formed in each of a plurality of intersection areas between a plurality of gate lines and a plurality of data lines, a built-in gate driver built into a non-display area of the panel, and configured to include a shift register including a plurality of scan stages which output a scan pulse, and a timing controller configured to generate first to nth clocks, a reset signal, and a start signal. In initial driving of the built-in gate driver, the timing controller continuously supplies a pulse of the reset signal to the plurality of scan stages while a pulse of the nth clock and a pulse of the first clock to a pulse of the (n−1) clock are each output once in a first frame.