Glass-Reinforced Embedded Bridge Package for Low Z-Height Interconnects
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Solution Overview
Problem
Organic-based Embedded Multi-die Interconnect Bridge (EMIB) technologies are limited to about 30 µm pitch for die-to-die connections due to technical challenges, and there is a need for semiconductor packages with low z-height and small footprint for high-performance computing and consumer electronic devices.
Innovation Solution
The development of IC packages with a glass reinforcement layer and embedded bridges, allowing for connections at pitches greater than or equal to 25 µm and incorporating a glass layer between IC dies with through vias for mechanical strength and low z-height, using hybrid bonding techniques and monolithic processes to enhance interconnect density and alignment precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If organic-based EMIB technology is used for die-to-die connections, then interconnect density can be increased, but the pitch is limited to about 30 µm due to technical challenges
Solution Approach 1:
The patent changes the material parameter from organic-based to glass-based interconnect bridge, enabling smaller pitch (≥25 µm) while maintaining reliability. The glass material properties (thermal stability, mechanical strength) fundamentally alter the achievable pitch and reliability characteristics compared to organic materials.
Solution Approach 2:
The patent employs composite material structures including glass layers combined with metal interconnects, and glass carriers integrated with die structures. This composite approach enables simultaneous achievement of small pitch, high reliability, and mechanical reinforcement.
2Manufacturing precision
If advanced packaging technologies like die embedding or silicon interposers are used, then package I/O counts and density can be significantly increased, but z-height and footprint increase
Solution Approach 1:
The patent extracts the interconnect bridge function from bulky organic EMIB structures and implements it using thin glass layers with embedded metal interconnects. This extraction reduces the z-height while maintaining high I/O density through the glass carrier architecture.
Solution Approach 2:
The patent uses thin glass films and layers (glass carrier, glass interconnect bridge) to achieve high I/O density with minimal z-height. The thin-film glass structures provide the necessary mechanical support and electrical interconnection without adding significant vertical dimension.
3Strength
If through vias are added to glass layer for mechanical reinforcement, then structural strength is improved, but manufacturing complexity increases
Solution Approach 1:
The patent forms through vias in the glass layer during the glass carrier preparation stage, before die attachment. This preliminary formation of vias integrates the via creation into the existing glass processing flow, avoiding additional complex steps after die assembly.
Solution Approach 2:
The patent merges the via formation process with the glass carrier fabrication process, and combines the mechanical reinforcement function with the electrical interconnection function. The through vias serve dual purposes: structural reinforcement and electrical routing, reducing overall device complexity.
Data Source
Figure 1A
Figure 1B
Figure 2~3B
AI summary
An integrated circuit (IC) package comprises a first IC die having first metallization features, a second IC die having second metallization features, and a third IC die having third metallization features. A glass layer is between the third IC die and both of the first IC die and the second IC die. A plurality of first through vias extend through the glass layer, coupling the third metallization features with first ones of the first metallization features and with first ones of the second metallization features. A plurality of second through vias extend through the glass layer. A dielectric material is around the third die and a package metallization is within the dielectric material. The package metallization is coupled to at least one of the first, second, or third IC die, and terminating at a plurality of package interconnect interfaces.