Glass Substrate with Copper-Tungsten Conductors for Thermal Management

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Solution Overview

Problem

As microelectronic devices miniaturize, the parasitic capacitance and resistance of metal interconnections increase, degrading chip performance, and existing flip-chip technologies face challenges with pre-testability, post-bonding inspection, and Temperature Coefficient of Expansion (TCE) matching, particularly when using glass as an interposer due to its lower thermal conductivity and difficulty in forming Through Glass Vias (TGVs).

Innovation Solution

A glass substrate with a solid glass core and copper-tungsten alloy conductors extending through it, along with dielectric and metal layers, is developed to address the performance issues by reducing parasitic effects and improving thermal management while maintaining low material costs and TCE matching.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If glass is used as an interposer material, then material cost is reduced and TCE matching is improved, but thermal conductivity is lowered and Through Glass Via formation becomes difficult

Engineering Contradiction:
Improvematerial costVSAvoidthermal conductivity
Core Design Contradiction:
Ease of manufactureVSTemperature

Solution Approach 1:

The patent employs copper-tungsten alloy conductors embedded in glass substrate to create a composite structure that combines the low cost and TCE matching of glass with the high thermal conductivity of metal alloys, resolving the thermal conductivity limitation of pure glass interposers

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The patent modifies the physical and chemical parameters of glass through controlled thermal processing and chemical composition adjustments to enable via formation while maintaining glass's inherent advantages of low cost and TCE matching with silicon

Inventive Principle:
Principle #35Parameter changes

2Productivity

If geometric dimensions of Integrated Circuits are scaled down, then cost per die is decreased and performance is improved, but parasitic capacitance and resistance of metal interconnections increase

Engineering Contradiction:
Improvecost per dieVSAvoidparasitic capacitance and resistance
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent changes the physical parameters of interconnection materials by using copper-tungsten alloys with optimized conductivity and dimensional stability, reducing parasitic effects in scaled-down circuits while maintaining cost efficiency

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent uses composite copper-tungsten conductor structures that combine the high conductivity of copper with the dimensional stability of tungsten, effectively reducing parasitic capacitance and resistance in miniaturized interconnections

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enhances chip performance by minimizing parasitic effects, improving thermal conductivity, and facilitating reliable interconnects, while maintaining cost-effectiveness and TCE matching, thus addressing the limitations of glass as an interposer material.

Implementation Method 1

multiple conductors extending through the solid glass core beginning at the first surface and ending at the second surface, wherein one of the conductors comprise a copper-tungsten alloy material

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 2

improving thermal conductivity

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS10453819B2Method for fabricating glass substrate package
Publication Date: 2019.10.22 MYW SEMITECH LLC
  • US10453819B2 patent drawing
  • US10453819B2 patent drawing
  • US10453819B2 patent drawing

AI summary

A substrate comprising a solid glass core having a first surface and a second surface opposed to the first surface; multiple conductors extending through the solid glass core beginning at the first surface and ending at the second surface, wherein one of the conductors has a third surface and a fourth surface, wherein the third surface and the first surface are substantially coplanar, wherein the second surface and the fourth surface are substantially coplanar, wherein one of the conductors comprise a copper-tungsten alloy material, wherein the solid glass core is directly contact with the conductor; and a first dielectric layer and a first metal layer formed at the first surface, wherein the first metal layer at the first surface is electrically coupled with one of the conductors.