Glass-Core EMIB Fan-Out Packaging for Die Warpage Control
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Solution Overview
Problem
Conventional die manufacturing techniques face challenges with die warpage due to CTE mismatches between materials in multi-die architectures, leading to reduced yield and exposure issues during planarization operations.
Innovation Solution
The use of a glass core that surrounds multiple dies, providing a dimensionally stable base and matching the CTE of various components, along with a glass carrier, to minimize warpage and facilitate effective assembly and interconnect formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple dies are interconnected with silicon bridges to provide heterogeneous-chip package functionality, then the desired functionalities are achieved, but the packaging complexity increases significantly
Solution Approach 1:
The patent introduces an interposer as an intermediary substrate between multiple dies, replacing complex silicon bridge interconnections. The interposer provides a standardized platform with pre-formed conductive structures that simplify the integration process while maintaining the ability to connect heterogeneous dies with different functionalities and specifications.
Solution Approach 2:
The interposer serves multiple functions simultaneously: it acts as a mechanical support structure, provides electrical interconnection between dies, enables thermal management, and offers a standardized interface for integrating different types of dies. This multi-functionality reduces overall packaging complexity compared to specialized interconnection solutions.
2Manufacturing precision
If CTE mismatch between die, die back film, build-up dielectric layers, and encapsulation materials is reduced, then die warpage is reduced, but material formulation limitations prevent complete elimination of warpage
Solution Approach 1:
The patent modifies the physical and chemical parameters of the interposer material, specifically selecting materials with thermal expansion coefficients that match those of the dies and surrounding structures. By carefully controlling the CTE parameter of the interposer, the patent achieves minimal warpage across temperature variations while maintaining compatibility with standard semiconductor materials.
Solution Approach 2:
The interposer is designed with homogeneous material composition and uniform structural properties throughout, ensuring consistent thermal and mechanical behavior. This homogeneity prevents differential expansion and contraction that would otherwise cause warpage, while still allowing integration with heterogeneous dies through standardized interfaces.
3Ease of operation
If planarization operation is performed to expose copper pillars and die backside interconnects, then interconnect accessibility is improved, but die warpage prevents simultaneous exposure without removing significant portions of the die
Solution Approach 1:
The patent performs planarization of the interposer surface before die attachment, creating a flat baseline structure. This preliminary planarization ensures that subsequent die mounting and encapsulation processes occur on a uniform surface, enabling proper exposure of interconnects without requiring excessive material removal from the dies themselves.
Solution Approach 2:
The interposer serves as a mediator that absorbs the planarization process, allowing the dies themselves to remain intact. The interposer's surface is planarized to provide a flat mounting surface and expose its own conductive structures, while the dies maintain their original geometry and can be attached without removing significant portions of their active areas.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces die warpage and improves yield by providing a stable base for assembly and allowing for precise interconnect formation, enabling the integration of advanced processing nodes like 7 nm gate lengths within electronics packages.
Implementation Method 1
matching the CTE of various components, along with a glass carrier, to minimize warpage
Data Source
AI summary
Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.