Glass-Core IC Package With Cavity Die for Low-Inductance Stacking
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Solution Overview
Problem
The miniaturization of implantable medical devices (IMDs) requires smaller and more compact electronic circuitry components, while maintaining high functionality and reducing the need for wire bonds to minimize parasitic inductance and resistive losses.
Innovation Solution
An integrated circuit package using a glass core layer with a cavity and patterned conductive layers on either side, allowing flip-chip connections and reduced package size, along with a method of forming such packages that enable stacking and improved dielectric properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional wire bond connections are used, then electrical connections are established, but parasitic inductance and resistive losses increase
Solution Approach 1:
The patent removes the wire bond interconnection layer entirely, extracting the harmful element (wire bonds) that causes parasitic inductance and resistive losses. The die is connected directly to the substrate through integrated contact structures, eliminating the intermediate wire bond connection that was responsible for energy losses.
Solution Approach 2:
The patent replaces the mechanical wire bond system with an integrated electrical connection system where the die contacts connect directly to substrate contact structures through conductive pathways within the substrate, substituting a mechanical interconnection approach with an integrated electrical field-based connection.
2Volume of moving object
If package dimensions are reduced for miniaturization, then device size decreases, but heat dissipation becomes more difficult
Solution Approach 1:
The patent transitions from planar heat dissipation to three-dimensional heat management by allowing heat to escape through multiple surfaces including the top surface of the die and lateral surfaces of the package. The stacked configuration and direct contact structures enable heat to dissipate in multiple spatial dimensions rather than being constrained to a single plane.
Solution Approach 2:
The patent segments the heat dissipation pathways by providing multiple independent thermal conduction routes through the substrate and contact structures, allowing heat to be distributed and dissipated through various pathways simultaneously, preventing thermal congestion in miniaturized packages.
3Reliability
If conventional packaging is used, then electrical connections are established, but package height remains large
Solution Approach 1:
The patent inverts the conventional packaging approach by placing the die in direct contact with the substrate without intermediate layers, and by having contact structures extend from the substrate up to meet the die rather than having wire bonds extend downward from the die. This inverted architecture eliminates the need for tall wire bond loops and reduces overall package height.
Solution Approach 2:
The patent merges the die contact structures with the substrate contact structures through direct integration, combining what were previously separate elements (wire bonds, bond pads, intermediate layers) into a unified direct connection system that reduces the vertical distance and eliminates unnecessary interfaces.
4Adaptability or versatility
If device functionality is increased, then performance improves, but device complexity increases
Solution Approach 1:
The patent creates multi-functional contact structures that simultaneously provide electrical connection, mechanical support, and thermal management functions. The integrated substrate and contact structure design serves multiple purposes, reducing the need for separate components and simplifying the overall package structure despite increased device functionality.
Solution Approach 2:
The patent employs a nested architecture where the die is positioned within a cavity or recess in the substrate, with contact structures nested within the substrate layers. This nested arrangement allows multiple functional elements to be compactly integrated without increasing overall package complexity, as each element is contained within or integrated with the structural framework.
Data Source
AI summary
Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The package includes a substrate having a glass core layer, where the glass core layer includes a first major surface, a second major surface, and a cavity disposed between the first major surface and the second major surface of the glass core layer. The package also includes a die disposed in the cavity of the glass core layer, an encapsulant disposed in the cavity between the die and a sidewall of the cavity, a first patterned conductive layer disposed adjacent the first major surface of the glass core layer, and a second patterned conductive layer disposed adjacent the second major surface of the glass core layer. The die is electrically connected to at least one of the first and second patterned conductive layers.