Glass-Core IC Package Cavity Layout for Low-Inductance Interconnects
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Solution Overview
Problem
The miniaturization of implantable medical devices (IMDs) requires more compact and efficient electronic circuitry packaging to reduce size and cost while maintaining performance, particularly in high-voltage applications where existing packaging technologies face challenges with size reduction and parasitic inductance, wire bond requirements, and heat dissipation.
Innovation Solution
The development of an integrated circuit package using a glass core layer with a cavity and patterned conductive layers, where a die is electrically connected to the conductive layers without wire bonds, and an encapsulant is used to reduce size and parasitic inductance, allowing for higher frequency operation and improved heat dissipation through multiple contacts and sides.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional packaging techniques are used, then device reliability is maintained, but device size and cost increase
Solution Approach 1:
The patent transitions from traditional planar packaging to a three-dimensional cavity-based structure. The die is positioned within a cavity formed in the substrate, allowing vertical stacking and multi-layer interconnects. This dimensional change enables compact packaging while maintaining electrical reliability through controlled via structures and layered conductive paths.
Solution Approach 2:
The patent implements nesting by placing the die inside a cavity formed within the substrate itself. The substrate acts as both the mounting platform and the packaging structure, with the cavity accommodating the die and surrounding encapsulant. This nested configuration eliminates the need for separate packaging housings, reducing overall size while protecting the die.
2Loss of energy
If wire bonds are used for electrical connection, then electrical connectivity is achieved, but parasitic inductance and device size increase
Solution Approach 1:
The patent extracts and eliminates the wire bond interconnect structure from the packaging system. Instead of using separate wire bonds to connect the die to external terminals, the design uses direct integrated interconnects formed within the substrate, removing the source of parasitic inductance and simplifying the overall device architecture.
Solution Approach 2:
The patent merges the function of separate wire bond interconnects with the substrate's integrated circuit traces and via structures. The electrical connection path is combined into the substrate's native conductive layers, creating a unified low-inductance pathway from die to package terminals without requiring discrete wire bonds.
3Volume of moving object
If compact packaging is implemented, then device size is reduced, but heat dissipation capability deteriorates
Solution Approach 1:
The patent applies local quality by creating high thermal conductivity pathways specifically at the die attachment region. The cavity structure and encapsulant are configured to provide enhanced thermal coupling between the die and the substrate's heat sink structures, while the surrounding packaging materials can have different properties optimized for their local functions. This localized thermal management enables compact packaging without compromising heat dissipation from the critical die region.
Data Source
AI summary
Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The package includes a substrate having a glass core layer, where the glass core layer includes a first major surface, a second major surface, and a cavity disposed between the first major surface and the second major surface of the glass core layer. The package also includes a die disposed in the cavity of the glass core layer, an encapsulant disposed in the cavity between the die and a sidewall of the cavity, a first patterned conductive layer disposed adjacent the first major surface of the glass core layer, and a second patterned conductive layer disposed adjacent the second major surface of the glass core layer. The die is electrically connected to at least one of the first and second patterned conductive layers.