Glass Core MIM Capacitor Thermal Expansion Mismatch
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Solution Overview
Problem
Miniaturized electronic devices face challenges with short circuits and reliability issues due to the integration of chip capacitors in organic core boards, which experience thermal expansion mismatches and impaired flatness, leading to potential open failures and reduced connection reliability.
Innovation Solution
A glass core-based electronic component with a MIM capacitor structure, featuring a conductor circuit, lower and upper electrodes made from metals like copper, nickel, and palladium, and a dielectric layer from materials like alumina, with the upper electrode's peripheral edge parallel to the conductor surface, ensuring electrical isolation and thermal stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If chip capacitors are embedded in organic core boards, then capacitor integration is achieved, but thermal expansion mismatch causes separation or cracking of the dielectric layer
Solution Approach 1:
The patent changes the material parameter of the core board from organic material to glass material, which has a coefficient of linear thermal expansion matching that of the dielectric layer. This parameter change eliminates the thermal expansion mismatch that causes separation or cracking during thermal cycling, thereby resolving the reliability issue while maintaining capacitor integration capability.
Solution Approach 2:
The patent uses glass material as the core board, which can be considered a composite material with properties tailored to match the dielectric layer's thermal expansion characteristics. This composite approach allows the core board to provide both structural support and thermal compatibility, preventing interface failures between the capacitor and board.
2Ease of manufacture
If the upper electrode peripheral edge aligns with the lower electrode peripheral edge, then manufacturing is simplified, but short circuit occurs due to dielectric layer separation
Solution Approach 1:
The patent applies preliminary anti-action by designing the upper electrode to extend beyond the lower electrode's peripheral edge. This preemptive design compensates for potential dielectric layer separation that could occur during thermal cycling, ensuring that the electrodes remain electrically isolated even if the dielectric layer shifts or cracks. This prevents short circuits before they can occur.
Solution Approach 2:
The extended upper electrode acts as a cushioning measure, providing an additional safety margin that accommodates thermal expansion and dielectric layer movement. This design ensures that even under thermal stress, the electrodes maintain proper spacing and electrical isolation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the reliability of miniaturized electronic components by preventing short circuits and maintaining connection reliability during thermal cycling, ensuring high electrical performance and reduced dimensional variation.
Implementation Method 1
a dielectric layer laminated on the lower electrode, and an upper electrode laminated on the dielectric layer
Implementation Method 2
the glass material has a small coefficient of linear thermal expansion (CTE) in the range of 2 ppm/K to 8 ppm/K matching silicon chips
Data Source
AI summary
An electronic component includes a glass base in which through holes are formed passing through both surfaces thereof; an insulating resin layer laminated on each of both surfaces of the glass base and including a copper plated layer formed therein; and a capacitor including a lower electrode formed on the copper plated layer, a dielectric layer laminated on the lower electrode, and an upper electrode laminated on the dielectric layer. In the electronic component, the upper electrode has a region that is parallel to the copper plated layer and is formed so as to be smaller than a region of the dielectric layer parallel to the surface of the copper plated layer or a region of the lower electrode parallel to the surface of the copper plated layer.