Glass-Core Semiconductor Package With Roughened Bonding Surfaces

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Solution Overview

Problem

Existing semiconductor packages face challenges in achieving structural stability and reducing manufacturing defects while meeting demands for miniaturization and integration of semiconductor chips.

Innovation Solution

A semiconductor package design incorporating a core portion made of glass with vertical connection terminals, and upper and lower buildup portions featuring insulating patterns and wiring patterns, where the core portion surfaces have increased roughness compared to the insulating patterns, enhancing adhesive strength and structural stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the core portion surface is made smooth, then the manufacturing process is simpler, but the adhesive strength between the core portion and insulating patterns is reduced

Engineering Contradiction:

Improvemanufacturing process simplicityVSAvoidadhesive strength

Core Design Contradiction:

Ease of manufactureVSStrength

Solution Approach 1:

The core portion surface is designed with a curved or rough profile instead of a flat surface. The surface includes protrusions and recesses that increase the contact area and mechanical interlocking with the insulating patterns, thereby enhancing adhesive strength without complicating the manufacturing process

Inventive Principle:

Principle #14Spheroidality (Curvature)

Solution Approach 2:

The core portion surface is designed with a porous or rough structure featuring protrusions and recesses. This increased surface roughness provides greater surface area and mechanical interlocking for the insulating patterns, improving adhesive strength while maintaining manufacturing feasibility

Inventive Principle:

Principle #31Porous materials

2Productivity

If the integration level of semiconductor chips is increased, then the functionality and speed are improved, but the structural stability and electrical characteristics of the package substrate become more difficult to maintain

Engineering Contradiction:

Improveintegration levelVSAvoidstructural stability

Core Design Contradiction:

ProductivityVSStability of the object's composition

Solution Approach 1:

The core portion surface is designed with a curved or rough profile instead of a flat surface. This increased surface roughness enhances the adhesive strength between the core portion and insulating patterns, providing improved structural stability that supports higher integration levels of semiconductor chips

Inventive Principle:

Principle #14Spheroidality (Curvature)

Solution Approach 2:

The package substrate is designed as a composite structure with a core portion made of one material and insulating patterns made of different materials. This composite structure allows optimization of each layer's properties to maintain structural stability and electrical characteristics while supporting higher integration levels

Inventive Principle:

Principle #40Composite materials

3Productivity

If the integration level of semiconductor chips is increased, then the functionality and speed are improved, but the manufacturing defects increase

Engineering Contradiction:

Improveintegration levelVSAvoidmanufacturing defects

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The core portion surface is designed with a curved or rough profile that enhances adhesive strength. This improved bonding reduces the risk of delamination and other manufacturing defects, thereby improving reliability while supporting higher integration levels of semiconductor chips

Inventive Principle:

Principle #14Spheroidality (Curvature)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design provides improved structural stability and reduces manufacturing defects by increasing adhesive strength between the core portion and insulating patterns, ensuring reliable electrical connections and enhanced package integrity.

Implementation Method 1

a surface roughness of the upper surface of the core portion and a surface roughness of the lower surface of the core portion are respectively larger than a surface roughness of an upper surface of the first insulating pattern and a surface roughness of a lower surface of the second insulating pattern

Methodology Applied

Scientific EffectSurface roughness effect: Adhesive

Data Source

PatentUS20250336832A1Semiconductor package and method for manufacturing the same

Publication Date: 2025.10.30 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor package includes a core portion including glass, a vertical connection terminal penetrating the core portion, an upper buildup portion at least partially covering an upper surface of the core portion, and a lower buildup portion at least partially covering a lower surface of the core portion, where the upper buildup portion includes a first insulating pattern at least partially covering the upper surface of the core portion and an upper surfaces of the vertical connection terminal and a first wiring pattern penetrating the first insulating pattern and connected to the vertical connection terminal, where the lower buildup portion includes a second insulating pattern at least partially covering the lower surface of the core portion and a lower surface of the vertical connection terminal, and a second wiring pattern penetrating the second insulating pattern and connected to the vertical connection terminals.