Glass-Core Packaging Substrate for Fine-Pitch High-Speed Interconnects
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Solution Overview
Problem
Current semiconductor packaging technologies face limitations in mounting high-performance and high-frequency semiconductor elements due to high resistance and dielectric constants in ceramic substrates, and limitations in miniaturizing conductive lines on resin substrates, while silicon substrates can cause parasitic element effects and organic substrates are not suitable for miniaturization.
Innovation Solution
A semiconductor apparatus using a glass substrate with core vias and a core distribution layer to connect conductive layers across the substrate, allowing for shorter electrical paths and improved signal transmission, and a packaging substrate with a glass core layer and upper conductive layers to facilitate efficient electrical connections between semiconductor elements and a motherboard.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a ceramic substrate is used for packaging, then the substrate provides structural support and protection, but the high resistance and high dielectric constant degrade electrical performance
Solution Approach 1:
The patent changes the material parameter of the substrate from ceramic to glass, which has different electrical properties (lower resistance and dielectric constant), thereby improving electrical performance while maintaining structural support functionality
Solution Approach 2:
The patent uses a composite structure combining glass substrate with conductive materials (copper, silver, or aluminum) in the through-via and distribution layer, creating a hybrid material system that optimizes both mechanical support and electrical conductivity
2Reliability
If a resin substrate is used to mount high-performance semiconductor elements, then the substrate allows for better electrical characteristics, but the pitch of conductive lines cannot be reduced further
Solution Approach 1:
The patent changes the substrate material from resin to glass, enabling further reduction in conductive line pitch while maintaining good electrical characteristics, as glass provides better dimensional stability and surface flatness for fine patterning
Solution Approach 2:
The patent introduces through-vias that extend vertically through the substrate, adding a third-dimensional conductive path that bypasses the planar distribution layer, thereby enabling shorter electrical paths and supporting higher density interconnections
3Reliability
If silicon substrate is used for packaging, then the electrical connection is improved, but parasitic element effects occur
Solution Approach 1:
The patent changes the substrate material from silicon to glass, which is electrically insulating, thereby eliminating parasitic element effects while maintaining good electrical connection through the use of dedicated conductive through-vias and distribution layers
4Reliability
If through-via is formed on glass substrate with conductive material, then the length of conductive lines is shortened, but the manufacturing complexity increases
Solution Approach 1:
The patent forms through-vias and applies conductive materials to the glass substrate before mounting the semiconductor element, preparing the electrical connection paths in advance to simplify subsequent assembly steps and ensure optimal electrical performance
Data Source
AI summary
A semiconductor apparatus includes a semiconductor element unit comprising one or more semiconductor elements, a packaging substrate, and a motherboard. The packaging substrate, connected to the semiconductor elements, includes a core layer and an upper layer disposed on the core layer. The core layer includes a glass substrate, a core via, and a core distribution layer. The glass substrate having a first surface and a second surface facing each other. A part of the core distribution layer connects electrically conductive layers of the first surface and an electrically conductive layer of the second surface through the core via penetrating through the glass substrate. A thickness of a thinner one among electrically conductive layers of the core distribution layer is the same as or greater than a width of a thinner one among the electrically conductive layers of the upper layer.