Glass-Core Packaging Substrate for Shorter High-Speed Signal Paths
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in achieving high-performance and high-frequency semiconductor element mounting due to high resistance and dielectric constants in ceramic substrates, and limitations in reducing wiring pitches in resin substrates.
Innovation Solution
A semiconductor apparatus utilizing a glass substrate as the core of the packaging substrate, featuring a core layer with a glass substrate and core via, and an upper layer with an electrically conductive layer connecting the core distribution layer and semiconductor element unit, thereby reducing electrical signal transmission length and improving electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a ceramic substrate is used for packaging, then structural strength is improved, but electrical resistance increases and dielectric constant increases
Solution Approach 1:
The patent employs a composite structure combining glass substrate with copper foil layers and resin encapsulation. The glass substrate provides structural strength while the copper foil layers provide low-resistance electrical pathways, and the resin encapsulation provides electrical insulation and protection. This composite approach resolves the contradiction by separating structural and electrical functions into different materials.
2Ease of manufacture
If a resin substrate is used for packaging, then ease of mounting high-performance semiconductors is improved, but wiring pitch reduction capability deteriorates
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional vertical interconnection through through-vias. The copper foil layers are stacked at different heights and connected vertically through the glass substrate, enabling complex electrical connections in the vertical dimension. This allows for reduced wiring pitches and improved signal transmission without compromising the ease of mounting semiconductors.
3Reliability
If through-via is formed on silicon or glass substrate with conductive material, then electrical characteristics are improved, but manufacturing complexity increases
Solution Approach 1:
The patent forms through-vias and fills them with conductive material during the substrate fabrication process before semiconductor mounting. This preliminary action integrates the electrical interconnection structure into the substrate itself, eliminating the need for complex post-assembly wiring operations and reducing overall manufacturing complexity while maintaining excellent electrical characteristics.
Data Source
AI summary
The embodiment relates to a packaging substrate and a semiconductor apparatus, including an element unit including a semiconductor element; and a packaging substrate electrically connected to the element unit; and it applies a glass substrate as a core of the packaging substrate, thereby can significantly improve electrical properties such as a signal transmission rate by connecting the semiconductor element and a motherboard to be closer to each other so that electrical signals are transmitted through as short a path as possible. Therefore, it can significantly improve electrical properties such a signal transmission rate, substantially prevent generating of parasitic element, and simplify a process of treatment for an insulating layer, and thus provides a packaging substrate applicable to a high-speed circuit.