Glass Core Via Buffer Layer for Warpage and Crack Resistance
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Solution Overview
Problem
The challenge in semiconductor packaging is warpage and stress-induced cracking due to thermal expansion mismatch between materials like Silicon and Copper, which affects the reliability and performance of glass core substrates used in integrated circuit apparatuses.
Innovation Solution
Incorporating a dielectric buffer layer, such as SiNx, SiOxNy, or SiC, between the glass core and metal vias/pads to reduce stress and improve adhesion, thereby enhancing the reliability and performance of glass core substrates by acting as an adhesion promoter and stress manager.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal vias and pads are directly contacted with glass core, then electrical connectivity is achieved, but stress-induced cracking and warpage occur due to thermal expansion mismatch
Solution Approach 1:
A dielectric buffer layer is introduced between the metal vias/pads and the glass core surface. This intermediary layer acts as a stress management interface that decouples the direct mechanical contact between materials with different thermal expansion coefficients (Silicon: 2.6 ppm/°C, ABF: ~39 ppm/°C, Copper: 17 ppm/°C), preventing stress transfer that would otherwise cause cracking in the fragile glass core during thermal cycling and manufacturing processes.
2Stability of the object's composition
If glass core is used as permanent substrate, then warpage is restricted and TTV requirement is maintained, but excess metallization stress causes micro cracks in glass core
Solution Approach 1:
The dielectric buffer layer serves as a protective intermediary that allows the glass core to maintain its structural stability and warpage control while simultaneously protecting it from the detrimental effects of metallization stress. The buffer layer absorbs and distributes the thermal expansion stress, preventing it from concentrating at the glass-metal interface and causing micro cracks.
3Reliability
If dielectric buffer layer is added between glass core and metal vias, then stress and cracking are reduced, but device complexity increases
Solution Approach 1:
The interface between the glass core and metal vias is segmented into distinct functional layers: the glass core layer, the dielectric buffer layer, and the metal via layer. This segmentation allows each layer to be optimized independently - the glass core for structural stability, the dielectric buffer for stress management and adhesion, and the metal via for electrical connectivity - thereby achieving improved reliability without proportionally increasing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dielectric buffer layer reduces warpage, improves I/O density, and increases the maximum current handling ability and reliability of metal vias, leading to better product yield and performance in semiconductor packaging.
Implementation Method 1
warpage and stress-induced cracking due to thermal expansion mismatch between materials like Silicon and Copper
Data Source
AI summary
In one embodiment, a substrate includes a glass core layer defining a plurality of holes between a first side of the glass core layer and a second side of the glass core layer opposite the first side and a conductive metal inside the holes of the glass core layer. The conductive metal electrically couples the first side of the glass core layer and the second side of the glass core layer. The substrate also includes a dielectric material between the conductive metal and the inside surfaces of the holes of the glass core layer.