Glass Core Via Layout for Flexible Die Floor Planning

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Solution Overview

Problem

Existing electronic packages face limitations in first level interconnect (FLI) bump pitch scaling due to restricted via pitches in organic substrates, leading to high substrate layer counts, manufacturing challenges, and reduced die floor plan flexibility, with TO interfaces often positioned on the die edge, limiting optimal die size and performance.

Innovation Solution

Implementing a glass core with through vias that match the FLI pitch, allowing seamless routing without the need for fan-out on the front side layers, and enabling flexible IO interface placement away from the die edge, thus reducing layer counts and improving manufacturing yield.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If LTH or PTH vias are used through the core, then signal routing is enabled, but via pitch is limited to 2×-4× FLI pitch, forcing front side fan-out and increasing substrate layer counts

Engineering Contradiction:

Improvevia pitchVSAvoidsubstrate layer count

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent changes the material parameter of the core from organic to glass, enabling via pitches at 0.5×-1.5× FLI pitch compared to the 2×-4× limitation with organic substrates. This parameter change in core material enables finer via spacing and eliminates the need for front side fan-out routing

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent extracts the routing function from the front side layers by enabling direct vertical routing through glass core vias. Signals route directly through the core without requiring fan-out on the front side, removing the routing bottleneck that forced high layer counts

Inventive Principle:

Principle #2Taking out (Extraction)

2Ease of operation

If TO interfaces are positioned on the die edge, then interface requirements are met, but die floor plan flexibility is limited and die size is increased

Engineering Contradiction:

Improveinterface positioningVSAvoiddie size

Core Design Contradiction:

Ease of operationVSArea of stationary object

Solution Approach 1:

The patent moves TO interfaces from the traditional die edge position to positions within the die interior, utilizing the vertical routing capability through glass core vias. This dimensional change in interface placement allows interfaces to be positioned anywhere on the die without requiring edge placement, optimizing die floor plan utilization

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Reliability

If front side fan-out routing is used, then signal routing is achieved, but routing density becomes very high and substrate layer count increases

Engineering Contradiction:

Improvesignal routingVSAvoidrouting density

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the fan-out routing function from the front side layers by enabling direct vertical routing through glass core vias. Signals that previously required complex fan-out routing on the front side now route directly through the core, eliminating the routing bottleneck and reducing front side routing density to minimal levels

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS12512396B2Flexible die to floor planning with bump pitch scale through glass core via pitch

Publication Date: 2025.12.30 INTEL CORP

AI summary

Embodiments disclosed herein include disaggregated die modules. In an embodiment, a disaggregated die module comprises a plurality of core logic blocks. In an embodiment, the disaggregated die module further comprises a first IO interface, where the first IO interface is adjacent to an edge of the disaggregated die module, and a second IO interface, where the second IO interface is set away from the edge of the disaggregated die module.