Glass Packaging Substrate Core Vias for Fine-Pitch Signal Routing
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Solution Overview
Problem
Current semiconductor packaging technologies face limitations in reducing wiring pitches and achieving high-speed, low-loss electrical connections due to the properties of ceramic and organic substrates, which hinder the miniaturization and performance of electronic devices.
Innovation Solution
A packaging substrate using a glass substrate with core vias and a core seed layer, where the core vias have a specific angle and thickness distribution, allowing for efficient electrical connectivity and reduced parasitic elements, enabling shorter signal paths and improved electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If ceramic substrate is used for packaging, then mechanical strength and thermal stability are improved, but electrical resistance and dielectric constant increase, limiting high-frequency performance
Solution Approach 1:
The patent uses a glass substrate as a composite material that combines the mechanical strength and thermal stability of ceramics with the electrical performance advantages of organic materials. The glass substrate has low dielectric constant and low loss tangent, enabling high-frequency signal transmission while maintaining structural integrity.
2Reliability
If resin substrate is used for packaging, then electrical performance and high-frequency mounting capability are improved, but wiring pitch reduction is limited
Solution Approach 1:
The patent changes the material parameter from organic resin to glass, which enables finer wiring pitch reduction. The glass substrate allows for smaller feature sizes and tighter wiring pitches while maintaining electrical performance, breaking the limitation of organic materials.
3Reliability
If through-via is formed on silicon substrate, then conductive line length is shortened and electrical characteristics are improved, but manufacturing complexity increases
Solution Approach 1:
The patent extracts the semiconductor element from the substrate and mounts it separately on the glass substrate. This eliminates the need for complex through-via formation in silicon substrates, as the glass substrate provides a planar mounting surface that simplifies the manufacturing process while maintaining short electrical connection lengths.
4Productivity
If conventional packaging substrate is used, then mass production is achievable, but device thickness and integration level cannot be reduced further
Solution Approach 1:
The patent employs a thin glass substrate that can be manufactured with precise thickness control. The glass substrate serves as a thin-film structure that enables reduced overall device thickness while maintaining mass production capability through standardized glass substrate manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The glass substrate packaging solution enhances signal transmission rates, reduces power loss, and facilitates mass production with improved economic efficiency by providing a more integrated and thinner packaging structure.
Implementation Method 1
a core layer having a core seed layer as a seed for forming an electrically conductive layer on a surface of the core vias
Data Source
AI summary
A packaging substrate includes a glass substrate comprising a first surface and a second surface facing each other, a plurality of core vias passing through the glass substrate in a thickness direction, and a core layer having a core seed layer as a seed for forming an electrically conductive layer on a surface of the core vias. The packaging substrate further includes an upper layer disposed on one surface of the core layer. The core layer includes a core distribution layer disposed on a surface of the glass substrate or a surface of the core via. The core distribution layer includes an electrically conductive layer at least a part of which electrically connects an electrically conductive layer of the first surface and an electrically conductive layer of the second surface through the core via.