Glass-Embedded Multi-Die Interconnect Bridge for Low-TTV Packaging
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Solution Overview
Problem
Monolithic integrated circuit (IC) fabrication faces limitations due to high costs, low insertion efficiency, and increased z-height in die-to-die interconnection, primarily due to the high total thickness variation (TTV) of organic dielectric materials used in IC packaging, which restricts the resolution of lithography and interconnect features.
Innovation Solution
The use of a glass substrate with embedded IC dies and finely patterned redistribution layer metallization for die bridging, allowing for direct interconnection between IC dies with superior flatness and thickness control compared to organic substrates, enabling efficient die-to-die interconnection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If organic dielectric material is used in IC packaging, then ease of manufacture is improved, but manufacturing precision deteriorates due to high total thickness variation
Solution Approach 1:
The patent changes the material parameter from organic dielectric to glass substrate, which fundamentally alters the thickness variation characteristics. Glass provides superior thickness uniformity and flatness control, directly resolving the manufacturing precision issue while maintaining manufacturability through established glass processing techniques.
Solution Approach 2:
The invention employs a composite structure where glass substrate serves as the base material with embedded IC dies and copper interconnects. This composite approach combines the dimensional stability of glass with the electrical functionality of semiconductor components, achieving both precision and ease of manufacture.
2Ease of manufacture
If organic dielectric material is used in IC packaging, then ease of manufacture is improved, but lithography resolution deteriorates due to large depth of focus requirements
Solution Approach 1:
By changing from organic dielectric to glass substrate, the patent improves the surface flatness and thickness uniformity parameters. This reduction in total thickness variation allows for a smaller depth of focus, thereby enabling higher lithography resolution for defining interconnect features.
3Adaptability or versatility
If die-to-die interconnection is implemented with organic substrate, then device functionality is improved, but z-height increases reducing interconnection efficiency
Solution Approach 1:
The patent changes the substrate material parameter to glass, which has superior flatness and thickness control. This enables the implementation of through-glass vias and embedded interconnects that reduce the vertical distance for signal transmission, thereby improving interconnection efficiency while maintaining device functionality.
Data Source
Figure 1
Figure 2~3B
Figure 4A~4B
AI summary
Multi-die packages including a glass substrate within a space between adjacent IC dies. Two or more IC die may be placed within recesses formed in a glass substrate. The IC die and glass substrate, along with any conductive vias extending through the glass substrate may be planarized. Organic package dielectric material may then be built up on both sides of the IC dies and glass substrate. Metallization features formed within package dielectric material built up on a first side of the IC die may electrically interconnect the IC dies to package interconnect interfaces that may be further coupled to a host with solder interconnects. Metallization features formed within package dielectric material built up on a second side of the first and second IC dies may electrically interconnect the first IC die to the second IC die.