Patterned Glass Dielectric Layers for Package Flatness Control
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Solution Overview
Problem
The reduction in size of mobile electronic devices requires tighter solder bump height and substrate thickness variation control, which is challenging due to the increased risk of flatness control issues with traditional encapsulating dielectric materials on silicon bridge dies, especially in EMIB architectures.
Innovation Solution
Implementing one or more permanent glass layers with redistribution layer (RDL) capability within organic non-EMIB or EMIB architectures, allowing for patterned glass dielectric layers with through-glass vias and RDLs to maintain flatness benefits and address substrate thickness variation control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional encapsulating dielectric materials are used on silicon bridge dies, then the packaging structure can be formed, but flatness control issues arise and substrate thickness variation increases
Solution Approach 1:
The patent changes the material parameter from traditional encapsulating dielectric materials to glass dielectric layers. Glass provides superior flatness control and thickness uniformity, directly resolving the contradiction between maintaining packaging structure integrity and controlling substrate thickness variation.
Solution Approach 2:
The patent employs composite material structures including glass dielectric layers combined with copper redistribution layers and silicon bridge dies. This composite approach leverages the flatness benefits of glass while integrating conductive pathways, solving both structural and electrical requirements simultaneously.
2Speed
If solder bump pitch is scaled down to sub 30 μm level, then higher speed and bandwidth are achieved, but thermal-compression bonding requires tighter solder bump height variation control
Solution Approach 1:
The patent performs preliminary planarization by using glass dielectric layers with inherent flatness properties before subsequent bonding processes. This pre-establishes a uniform surface that reduces solder bump height variation, enabling tighter control required for sub-30 μm pitch high-speed applications.
3Manufacturing precision
If glass layers with RDL capability are implemented, then flatness benefits are maintained and substrate thickness variation is controlled, but device complexity increases
Solution Approach 1:
The patent implements multi-functional glass dielectric layers that simultaneously provide electrical insulation, mechanical flatness support, and serve as a substrate for copper redistribution layers. This consolidation of multiple functions into single layers reduces overall device complexity while maintaining precision control.
Solution Approach 2:
The patent merges the dielectric function, mechanical support function, and interconnect support function into integrated glass-copper composite structures. By combining these functions rather than using separate layers, the overall packaging structure complexity is reduced while achieving superior thickness control.
Data Source
AI summary
Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to a manufacturing process flow for packages that include one or more glass layers that include patterning features, such as electrically conductive traces, RDLs, and vias within the packages. In embodiments, a package may include a glass layer with a first side and a second side opposite the first side, where the glass layer is a dielectric layer. The package may include another layer coupled with the first side of the glass layer, and a pattern on the second side of the glass layer to receive a deposited material in at least a portion of the pattern.