Glass Frame Multichip Packaging Without TSV Interposers
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Solution Overview
Problem
Current multichip interconnecting packaging structures using TSV interposers are costly, voluminous, and limit design freedom due to their thickness, making it difficult to achieve high-density, miniaturized, and lightweight packaging with low integration levels.
Innovation Solution
A multichip interconnecting packaging structure utilizing a glass frame with embedded chip connecting devices and via posts, allowing for conductive communication between chips and a substrate without the need for a TSV interposer, enabling high-density integration and flexible design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a TSV interposer is used to achieve chip-to-chip interconnection, then interconnection functionality is achieved, but production cost increases and packaging volume increases
Solution Approach 1:
The patent extracts the chip connecting device from the traditional TSV interposer structure and embeds it directly into the packaging carrier board. This eliminates the need for a separate thick interposer layer, thereby reducing packaging module volume while maintaining interconnection functionality through the embedded device and its terminals that connect to outer layer line pads.
Solution Approach 2:
The chip connecting device is nested within the packaging carrier board structure, with the device embedded in a cavity and surrounded by insulating material. This nesting approach integrates the interconnection function directly into the carrier board, reducing overall packaging volume compared to the external TSV interposer approach.
2Reliability
If a TSV interposer is used to achieve chip-to-chip interconnection, then interconnection functionality is achieved, but production cost increases
Solution Approach 1:
The patent merges the chip connecting device with the packaging carrier board into a single integrated structure. The device is embedded during the carrier board manufacturing process rather than requiring separate fabrication and assembly of a TSV interposer, thereby simplifying the manufacturing process and reducing production costs while maintaining interconnection functionality.
Solution Approach 2:
The packaging carrier board is designed to serve multiple functions: it provides mechanical support, electrical interconnection through embedded devices, and thermal management. This multi-functionality eliminates the need for separate TSV interposers, reducing production complexity and cost while achieving the required interconnection functionality.
3Reliability
If a TSV interposer with thickness is used, then interconnection is achieved, but design freedom is limited
Solution Approach 1:
The patent employs a flexible embedding approach where the chip connecting device can be positioned at various locations within the carrier board cavity, and terminals can be routed to different outer layer pads. This dynamic configurability provides design freedom for different chip layouts and interconnection patterns, unlike the fixed thick interposer structure.
Solution Approach 2:
The embedding depth, cavity position, and terminal routing can be locally optimized for each specific application requirement. This allows tailored design freedom for different packaging scenarios while maintaining reliable interconnection, contrasting with the uniform thick interposer approach that limits design flexibility.
Data Source
AI summary
A multichip interconnecting packaging structure includes a glass frame, a first line layer and a second line layer respectively provided on the first surface and the second surface of the glass frame, a first via post penetrating through the glass frame, a cavity penetrating through the glass frame, a chip connecting device embedded in the cavity, a first insulating layer filling the cavity to cover the chip connecting device, and a first chip and a second chip provided on the surface of the first line layer, wherein a terminal of the chip connecting device is connected to the first line layer, the first line layer and the second line layer are in conductive communication through the first via post, the first chip and the second chip are connected to the chip connecting device through the first line layer to interconnect the first chip with the second chip.