Glass Frame Package Substrate for Low-Loss Chip Embedding
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Solution Overview
Problem
Current semiconductor packaging using organic dielectric materials results in high electrical signal loss and thermal expansion mismatch issues, leading to reliability problems and the risk of chip cracking during the press-fitting process.
Innovation Solution
A package substrate manufacturing method utilizing a glass frame with a low dielectric constant and wide coefficient of thermal expansion, replacing press-fitting with a coating process, and forming a metal pillar and circuit layer to reduce signal loss and enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If organic dielectric material (polyimide, epoxy resin, or bismaleimide-triazine resin with glass fibers) is used for packaging, then the packaging process is simple and cost-effective, but the dielectric constant and dielectric loss are high causing long delay time and high electrical signal loss
Solution Approach 1:
The patent changes the material parameter from organic dielectric material to low-Dk glass material, fundamentally altering the dielectric constant and dielectric loss characteristics to reduce electrical signal loss and improve signal transmission speed
Solution Approach 2:
The patent uses composite low-Dk glass material combined with specific packaging materials that have low dielectric constant and low dielectric loss, creating a composite structure that optimizes both electrical performance and mechanical properties
2Reliability
If organic dielectric material is used for packaging, then the packaging process is straightforward, but the coefficient of thermal expansion mismatches with embedded electronic components causing reliability problems under extreme conditions
Solution Approach 1:
The patent changes the thermal expansion parameter by selecting low-Dk glass material with specific thermal expansion coefficients that match embedded electronic components, improving reliability under extreme temperature conditions
Solution Approach 2:
The patent applies different materials with locally optimized properties - using low-Dk glass material in specific regions where thermal expansion matching is critical, while maintaining overall packaging structure integrity
3Reliability
If press-fitting method is used for packaging, then the packaging process is simple and efficient, but there is a risk of cracking the chip during the press-fitting process
Solution Approach 1:
The patent replaces the mechanical press-fitting system with a coating-based packaging method, eliminating the high mechanical stress that causes chip cracking while maintaining packaging effectiveness
Solution Approach 2:
The patent applies a protective coating layer before final packaging, providing cushioning and stress distribution that prevents chip cracking during the packaging process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method reduces electrical signal transmission loss, improves signal speed, enhances thermal expansion matching, decreases the risk of chip cracking, and lowers manufacturing costs by using a glass frame and coating process.
Implementation Method 1
coating a dielectric layer to an upper surface of the glass frame, the through hole and the chip embedding cavity
Implementation Method 2
the circuit layer being arranged on the upper surface and a lower surface of the glass frame and being connected to the electronic component and the metal pillar
Data Source
AI summary
A package substrate includes: a glass frame having a through hole and a chip embedding cavity; an electronic component arranged in the chip embedding cavity; a dielectric layer filled on an upper surface of the glass frame and in the chip embedding cavity; a metal pillar passing through the through hole; a circuit layer arranged on the upper surface and/or a lower surface of the glass frame and connected to the electronic component and the metal pillar; and a solder mask arranged on a surface of the circuit layer and having a pad which is connected to the circuit layer.