Glass Interposer Chip Package for Dense Low-Parasitic Connections
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Solution Overview
Problem
As microelectronic devices are miniaturized, the parasitic capacitance and resistance of metal interconnections increase, degrading chip performance, and existing flip-chip technologies face challenges with pre-testability, post-bonding inspection, and Temperature Coefficient of Expansion (TCE) matching, especially when using glass as an interposer between IC chips and printed circuit boards.
Innovation Solution
A glass substrate with multiple metal conductors and bumps is used, where the conductors are connected to contact pads through bumps, and the substrate is fabricated using a process involving thermal resistance layers, molds, and glass layers to form metal traces and plugs, enabling efficient interconnection and reducing parasitic effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If glass is used as an interposer substrate, then material cost is reduced and CTE matching with silicon is improved, but thermal conductivity is lower compared to silicon
Solution Approach 1:
The patent employs a composite structure combining glass substrate with metal interconnection layers (copper, aluminum, or tungsten) and dielectric materials. This composite approach allows the glass to provide low cost and CTE matching while the metal layers provide enhanced thermal conductivity pathways and electrical interconnections, effectively resolving the thermal conductivity limitation of pure glass
2Productivity
If metal interconnection dimensions are scaled down, then cost per die is decreased and integration is improved, but parasitic capacitance and resistance increase
Solution Approach 1:
The patent utilizes copper or aluminum metal layers with controlled thickness and width parameters, along with low-k dielectric materials having specific dielectric constants, to optimize the balance between miniaturization and parasitic effects. By carefully controlling the geometric parameters and material properties, the design achieves reduced cost through scaling while managing parasitic capacitance and resistance through material selection and dimensional optimization
3Productivity
If flip-chip technology is used with area array, then interconnection density is increased and inductance is reduced, but pre-testability and post-bonding inspection become challenging
Solution Approach 1:
The patent divides the interconnection structure into discrete, addressable elements including individually addressable heating elements, temperature sensors, and test pads on the glass substrate. This segmentation allows for pre-bonding electrical testing and post-bonding inspection of individual interconnections, resolving the testability challenge while maintaining high interconnection density through the array structure
Data Source
AI summary
A display device comprises a display panel substrate and a glass substrate over said display panel substrate, wherein said display panel substrate comprises multiple contact pads, a display area, a first boundary, a second boundary, a third boundary and a fourth boundary, wherein said display area comprises a first edge, a second edge, a third edge and a fourth edge, wherein said first boundary is parallel to said third boundary and said first and third edges, wherein said second boundary is parallel to said fourth boundary and said second and fourth edges, wherein a first least distance between said first boundary and said first edge, wherein a second least distance between said second boundary and said second edge, a third least distance between said third boundary and said third edge, a fourth distance between said fourth boundary and said fourth edge, and wherein said first, second, third and fourth least distances are smaller than 100 micrometers, and wherein said glass substrate comprising multiple metal conductors through in said glass substrate and multiple metal bumps are between said glass substrate and said display panel substrate, wherein said one of said metal conductors is connected to one of said contact pads through one of said metal bumps.