Glass Interposer CPO Package Layout for Dense Optical-Electrical Integration

The patent replaces expensive TSV interposers with a cost-effective build-up package substrate approach. Instead of using costly silicon interposers with TSV technology, the invention employs a multi-layer copper foil and dielectric structure that achieves comparable or superior connection density at significantly lower manufacturing cost, making the solution economically viable for mass production

The patent changes the fundamental parameters of the interconnection approach by transitioning from vertical TSV holes in silicon to planar multi-layer copper traces on a build-up substrate. This parameter change includes using thinner dielectric layers (5-20 micrometers) and smaller line widths (5-20 micrometers) to achieve high density without the complexity and cost of TSV processing

The patent transitions from a two-dimensional side-by-side arrangement of ASIC, EIC, and PIC assemblies to a three-dimensional stacked configuration. By utilizing vertical stacking with multiple layers and interlayer connections, the invention achieves high functional integration while dramatically reducing the footprint area of the package substrate

The patent employs a nested arrangement where multiple functional assemblies are integrated within a compact hierarchical structure. The build-up package substrate with its multi-layer copper and dielectric structure acts as a nested framework that accommodates multiple assemblies in a space-efficient manner, with redistribution layers and vias providing interconnections between stacked components