Glass Interposer With Embedded Dies for Fine-Pitch IC Packaging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional approaches for coupling semiconductor dies in multichip packages face challenges in achieving fine pitch interconnect density, leading to high costs and low manufacturing yields, particularly in assembling EMIBs due to stringent via-to-pad overlay requirements and increased I/O density, with high-cost components being scrapped if any portion of the substrate is non-functional.
Innovation Solution
Incorporating a glass layer with vias extending through it for front-to-back connections, along with a conductive through-glass via (TGV) and a redistribution layer (RDL), allowing for finer pitch and reduced package dimensions, and integrating EMIBs into an interposer that electrically couples to the package substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional approaches are used for coupling semiconductor dies in multichip packages, then assembly can be performed with standard processes, but fine pitch interconnect density cannot be achieved, leading to high costs and low manufacturing yields
Solution Approach 1:
The patent transitions from planar 2D interconnect routing to 3D vertical routing through through-silicon vias (TSVs) and embedded die structures. This dimensional change enables fine pitch interconnect density by routing signals vertically through the substrate rather than laterally across the surface, achieving higher interconnect density without increasing lateral pitch constraints.
Solution Approach 2:
The patent embeds semiconductor dies within cavities formed in the substrate, creating a nested structure where dies are positioned inside recesses. This nesting approach allows multiple dies to be coupled in a compact arrangement with improved alignment and reduced pitch requirements, enabling fine pitch interconnect density while maintaining manufacturing feasibility.
2Manufacturing precision
If EMIBs are assembled with stringent via-to-pad overlay requirements, then fine pitch interconnect density is achieved, but cost increases and manufacturing yield decreases due to high scrappage of non-functional substrates
Solution Approach 1:
The patent forms through-silicon vias and cavity structures in the substrate before embedding the semiconductor dies. This preliminary structuring establishes precise alignment features and mechanical constraints that guide die placement, ensuring via-to-pad overlay accuracy is achieved during assembly without requiring expensive post-alignment adjustments or scrappage of misaligned substrates.
Solution Approach 2:
The patent introduces an intermediate substrate structure with pre-formed vias and cavities that acts as a mediator between the package substrate and the semiconductor dies. This intermediate structure provides mechanical support, electrical interconnection, and alignment reference, enabling precise via-to-pad overlay while simplifying the assembly process and reducing manufacturing cost.
3Manufacturing precision
If I/O density is increased to achieve finer pitch, then interconnect density improves, but package complexity increases and manufacturing yield decreases
Solution Approach 1:
The patent resolves the complexity issue by transitioning from 2D lateral interconnect routing to 3D vertical routing through TSVs and embedded die structures. This dimensional change allows high interconnect density to be achieved through vertical stacking and multi-layer routing rather than increasing lateral I/O count, thereby maintaining simpler package architecture while achieving fine pitch interconnect density.
Data Source
AI summary
Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a first layer with an insulating material and a die surrounded by the insulating material; a second layer on the first layer, the second layer including a dielectric material and a conductive pathway through the dielectric material, wherein the conductive pathway includes a conductive trace and a conductive via having an inverted trapezoidal shape; and a third layer on the second layer, the third layer including a glass layer and a conductive through-glass via (TGV), wherein the conductive TGV is electrically coupled to the conductive pathway and the die is electrically coupled to the conductive TGV by the conductive pathway.