Glass Interposer Package Layout for Dense ASIC-PIC-EIC Integration
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Solution Overview
Problem
Current high-density packaging carriers for high-performance computing (HPC) fail to meet stringent line width and spacing requirements, and the use of through silicon via interposers is expensive, while existing build-up package substrates cannot reduce the area of the package substrate due to the side-by-side placement of ASIC, EIC, and PIC assemblies.
Innovation Solution
A package structure utilizing a glass interposer with through glass vias and thin film redistribution layers to integrate ASIC, EIC, and PIC assemblies, along with an optical fiber assembly, achieving high-density and cost-effective integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a through silicon via interposer is added to the build-up package substrate, then the line width and line spacing requirements are met, but the manufacturing cost increases significantly
Solution Approach 1:
The patent changes the substrate material from silicon to glass, which fundamentally alters the manufacturing parameters. Glass substrates enable direct formation of fine-pitch interconnects through standard PCB processes like laser drilling and electroplating, achieving the required line width and spacing without expensive TSV technology. This material parameter change resolves the contradiction by providing a cost-effective pathway to high precision.
Solution Approach 2:
The patent employs a glass interposer that can be manufactured using conventional, cost-effective processes rather than expensive silicon TSV technology. The glass substrate serves as a disposable intermediate carrier that enables precise routing and can be integrated with standard packaging processes, significantly reducing manufacturing costs while meeting precision requirements.
2Reliability
If ASIC assembly, EIC assembly, and PIC assembly are placed side by side, then electrical and optical connections are achieved, but the package substrate area increases
Solution Approach 1:
The patent transitions from a purely planar side-by-side arrangement to a three-dimensional configuration by implementing vertical stacking of assemblies on the glass interposer. The glass substrate provides multiple routing layers and vertical interconnect structures that enable assemblies to be positioned at different heights, reducing the horizontal footprint while maintaining all necessary electrical and optical connections.
Solution Approach 2:
The patent employs a nested arrangement where the photonic integrated circuit assembly is positioned within a cavity of the glass interposer, and the electronic integrated circuit assembly is stacked above it. This nested doll-like configuration allows multiple assemblies to occupy overlapping vertical spaces, significantly reducing the overall package substrate area while preserving all connection pathways.
3Area of stationary object
If a glass interposer with cavity is used to stack assemblies vertically, then the package substrate area is reduced, but the manufacturing complexity increases
Solution Approach 1:
The patent changes the substrate material to glass, which possesses unique properties that simplify the manufacturing of complex three-dimensional structures. Glass can be easily laser-drilled, electroplated, and molded into complex shapes including cavities and through-holes using standard PCB processes. This material parameter change reduces manufacturing complexity compared to forming similar structures in traditional substrates.
Solution Approach 2:
The glass interposer is designed with self-aligning features and standardization that enable automated assembly processes. The cavity structures and through-holes are formed with tolerances that allow for self-alignment during assembly, reducing the need for complex alignment procedures and manual intervention, thereby managing manufacturing complexity despite the three-dimensional configuration.
Data Source
AI summary
A package structure includes a circuit board, a glass interposer, a first film redistribution layer, a second film redistribution layer, an application specific integrated circuit (ASIC) assembly, a photonic integrated circuit (PIC) assembly, an electronic integrated circuit (EIC) assembly and an optical fiber assembly. The glass interposer includes a cavity and a through glass via (TGV). The first film redistribution layer and the second film redistribution layer are respectively disposed on an upper surface and a lower surface of the glass interposer and electrically connected to the TGV. The ASIC assembly is disposed on and electrically connected to the first film redistribution layer. The PIC assembly is disposed in the cavity and electrically connected to the first film redistribution layer. The EIC assembly is stacked and electrically connected to the PIC assembly. The optical fiber assembly is disposed on the glass interposer and optically connected to the PIC assembly.