Glass-Substrate Leadless Package for Integrated Die Isolation

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Solution Overview

Problem

Conventional isolation methods for semiconductor circuits face limitations such as bulkiness, limited bandwidth, susceptibility to environmental factors, and complexity in leadless packaging, which pose challenges in maintaining adequate creepage and clearance distances, and introduce reliability risks.

Innovation Solution

A leadless package design utilizing a glass substrate with integrated capacitive and inductive coupling between semiconductor dies, eliminating the need for external components and exposed pads, and enhancing insulation through electromagnetic compatibility measures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional isolation components (optocouplers, capacitors, transformers) are used, then isolation between voltage levels is achieved, but the device becomes bulky and has limited bandwidth

Engineering Contradiction:

Improveisolation performanceVSAvoiddevice size

Core Design Contradiction:

ReliabilityVSVolume of moving object

Solution Approach 1:

The patent merges multiple isolation functions (capacitive coupling, inductive coupling, and insulation) into a single integrated leadless package structure. The glass substrate integrates the capacitive insulator and inductive elements, eliminating the need for separate external components and achieving both compact size and effective isolation.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent implements nesting by placing the capacitive insulator and inductive elements within the leadless package structure itself. The first and second capacitive insulators are nested between the semiconductor die and the leadless package, while the inductive elements are integrated into the package substrate, creating a compact nested arrangement that provides both isolation and electromagnetic shielding.

Inventive Principle:

Principle #7Nested doll (Nesting)

2Volume of moving object

If integrated isolators are used within semiconductor components, then device compactness is improved, but insulation distance is limited due to metal layer constraints

Engineering Contradiction:

Improvedevice sizeVSAvoidinsulation performance

Core Design Contradiction:

Volume of moving objectVSReliability

Solution Approach 1:

The patent changes the insulation parameter by using glass material with a breakdown voltage of at least 500 Vrms/μm, which provides superior insulation performance compared to traditional metal layer constraints. This material parameter change enables adequate creepage and clearance distances while maintaining a compact leadless package structure.

Inventive Principle:

Principle #35Parameter changes

3Area of stationary object

If leadless package configuration is used, then footprint is reduced and thermal management is improved, but manufacturing complexity increases due to lead frame split requirements

Engineering Contradiction:

ImprovefootprintVSAvoidmanufacturing complexity

Core Design Contradiction:

Area of stationary objectVSEase of manufacture

Solution Approach 1:

The patent extracts the problematic lead frame split requirement from the leadless package design. By using a glass substrate with integrated capacitive and inductive elements, the design eliminates the need for complex lead frame modifications, simplifying the manufacturing process while maintaining the compact footprint and thermal management benefits of leadless packaging.

Inventive Principle:

Principle #2Taking out (Extraction)

4Reliability

If adequate creepage and clearance distances are maintained in leadless packages, then electrical breakdown is prevented, but available space is reduced

Engineering Contradiction:

Improveelectrical breakdown preventionVSAvoidavailable space

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent uses composite material strategies by combining glass substrate material with specific dielectric properties with integrated capacitive and inductive elements. The glass material provides high breakdown voltage (at least 500 Vrms/μm), enabling adequate creepage and clearance distances to be achieved within the compact leadless package footprint without compromising available space for other components.

Inventive Principle:

Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The glass substrate provides robust isolation from environmental factors, simplifies manufacturing, and enhances reliability and longevity of semiconductor devices by eliminating the need for additional coatings and reducing manufacturing complexities.

Implementation Method 1

When glass is utilized as a substrate material, it offers several advantages. Firstly, glass, being an insulating material, effectively isolates the internal components of the semiconductor device from the external environment.

Methodology Applied

Scientific EffectElectrical insulation: Dielectric

Implementation Method 2

a bottom electrically conductive plate provided in or at said bottom side of said glass substrate, wherein said bottom electrically conductive plate is oriented such that a capacitive and an inductive coupling is provided between: said first electrically conductive plate and said bottom electrically conductive plate

Methodology Applied

Scientific EffectCapacitive coupling: Capacitance

Implementation Method 3

Methodology Applied

Scientific EffectInductive coupling: Electromagnetic Induction

Data Source

PatentEP4668327A1A leadless package comprising a first and a second semiconductor die, wherein a galvanic coupling is provided between those semiconductor dies, as well as a corresponding method

Publication Date: 2025.12.24 NEXPERIA BV

Figure 1a~1b
Figure 2a~2c
Figure 2d~2f

AI summary

A leadless package, comprising: a glass substrate; first and second electrically conductive interconnect route layers provided on a top side of said glass substrate, wherein the first and second electrically conductive interconnect route layers are isolated from each other; first and second electrically conductive top plates provided on said top side of said glass substrate; a first semiconductor die having at least two terminals, wherein a first of said two terminals is connected to the first electrically conductive interconnect route layer and a second of said at least two terminals is connected to said first electrically conductive top plate; a second semiconductor die having at least two terminals, wherein a first of said two terminals is connected to the second electrically conductive interconnect route layer and a second of said at least two terminals is connected to said second electrically conductive top plate; a first via through said glass substrate for enabling an electrical connection from a bottom side of said glass substrate to said first electrically conductive plate; a second via through said glass substrate for enabling an electrical connection from said bottom side of said glass substrate to said second electrically conductive plate; a bottom electrically conductive plate provided in or at said bottom side of said glass substrate, wherein said bottom electrically conductive plate is oriented such that at least one capacitive coupling and at least one inductive coupling is provided between: said first electrically conductive plate and said bottom electrically conductive plate, and said second electrically conductive plate and said bottom electrically conductive plate.