Glass-Substrate Multichip Packaging for Fine-Pitch Die Bonding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current IC packaging technologies face challenges such as high cost, low insertion efficiency, and increased z-height due to high total thickness variation (TTV) and depth of focus (DOF) limitations, which hinder effective die-to-die interconnection and reduce factory capacity.
Innovation Solution
The use of a glass substrate with conductive through-glass vias (TGVs) allows for direct bonding of IC dies, eliminating the need for an interconnect bridge die and enabling high interconnect density, with metallization features directly bonded to TGVs or soldered, facilitating low TTV and good dimensional stability for multi-chip devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If organic dielectric material is used for package substrate, then ease of manufacture is improved, but manufacturing precision deteriorates due to high total thickness variation and depth of focus requirements
Solution Approach 1:
The patent changes the material parameter from organic dielectric to glass substrate, which fundamentally alters the thickness variation characteristics. Glass provides superior dimensional stability and lower TTV, enabling high-resolution lithography for package metallization features while maintaining ease of manufacture through established glass processing techniques.
Solution Approach 2:
The patent employs a composite structure combining glass substrate with organic dielectric layers and metallization features. The glass substrate serves as the foundational layer providing dimensional stability, while organic dielectric materials are used in specific functional layers, creating a hybrid structure that leverages the advantages of both material types.
2Reliability
If die-to-die interconnection is implemented, then electrical performance is improved, but device complexity increases due to additional interconnect bridge die
Solution Approach 1:
The patent merges the interconnect function directly into the package substrate by forming metallization features and vias within the glass substrate itself. This eliminates the need for a separate interconnect bridge die, as the substrate simultaneously serves as both the mechanical support and the electrical interconnection medium, thereby reducing device complexity while maintaining electrical performance.
Solution Approach 2:
The glass substrate is designed to perform multiple functions: it provides mechanical support, electrical insulation, thermal management, and electrical interconnection through integrated metallization features and vias. This multi-functionality eliminates the need for separate dedicated interconnect components, reducing overall device complexity.
3Reliability
If bump pitch is reduced for higher interconnect density, then electrical performance is improved, but manufacturing precision requirements increase due to solder bump thickness variation
Solution Approach 1:
The patent replaces the traditional mechanical solder bump interconnection system with a direct metallization bonding approach. Metallization features are formed directly on the glass substrate and bonded to corresponding metallization on the IC die, eliminating the need for solder bumps and their associated thickness variation issues. This enables reduced bump pitch without proportionally increased manufacturing difficulty.
4Manufacturing precision
If planarization and advanced lamination technologies are used to reduce BTV, then manufacturing precision is improved, but productivity deteriorates due to reduced factory capacity
Solution Approach 1:
The patent performs planarization and metallization feature formation on the glass substrate before IC die attachment. This preliminary action allows the substrate to be prepared in advance with precise metallization patterns, and then multiple IC dies can be attached in parallel without requiring subsequent planarization steps, thereby maintaining both manufacturing precision and high productivity.
Data Source
AI summary
Multi-chip/die device including a logic IC die facing a first side of a glass substrate and a memory IC die facing, and coupled to, the logic IC die. First ones of first metallization features of the logic IC die are coupled to through-glass vias extending through a thickness of the glass substrate. The memory IC die is coupled to second ones of the first metallization features, either directly or by way of other through-glass vias. The logic IC die and/or memory IC die may be directly bonded to the through-glass vias or may be attached by solder. The logic IC die or memory IC die may be embedded within the glass substrate. Through-glass vias within a region beyond an edge of the memory IC die may couple the logic IC die to a host component either through a routing structure built up adjacent the memory IC die, or through solder features attached to the glass substrate adjacent to the memory IC die.