Glass Patch Bridge Architecture for Ultrafine Pitch Multi-Die Packaging
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Solution Overview
Problem
Existing semiconductor packaging technologies face challenges in achieving ultrafine pitch interconnects and efficient multi-die integration due to limitations in bridge die bump pitches, leading to increased costs, interconnect physical areas, and complex assembly processes.
Innovation Solution
The implementation of a multi-die ultrafine pitch patch architecture using a glass patch with through glass vias (TGVs) and a high-density packaging (HDP) substrate, eliminating solder-based connections and incorporating a bridge with adhesive bonding, which reduces the need for silicon interposers and enhances thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solder-based embedded bridge die connections are used, then interconnect functionality is achieved, but bridge die bump pitches are limited and assembly complexity increases
Solution Approach 1:
The patent extracts and eliminates the solder-based connection mechanism from the bridge die interconnect system. Instead of using solder bumps and reflow processes, the invention employs direct bonding interfaces between bridge dies and package substrate, removing the soldering step and its associated complexity while maintaining reliable electrical and mechanical connections
Solution Approach 2:
The patent introduces an intermediary bonding layer or interface structure between the bridge die and package substrate that enables direct bonding without solder. This intermediary mechanism facilitates reliable interconnect functionality through controlled bonding processes while avoiding the limitations of solder-based bump pitch constraints
2Quantity of substance
If multiple extraneous bridge dies are embedded to accommodate multi-die interconnects, then interconnect density increases, but package assembly time and substrate flatness control requirements increase
Solution Approach 1:
The patent merges multiple bridge die functions into a more integrated architecture where bridge dies are strategically positioned and bonded directly to the package substrate in fewer discrete steps. This consolidation maintains high interconnect density while reducing the total number of separate assembly operations required
Solution Approach 2:
The patent employs preliminary bonding preparations and pre-aligned bridge die structures that are ready for direct attachment to the package substrate. This preliminary positioning and preparation enables faster assembly by eliminating iterative alignment and adjustment steps during the bonding process
3Reliability
If solder-based bridge die connections are used, then electrical interconnect is achieved, but bump pitch scaling is limited
Solution Approach 1:
The patent replaces the mechanical solder bump system with a direct bonding interface that does not rely on solder material properties. This substitution enables smaller pitch dimensions because the bonding mechanism is not constrained by solder reflow process limitations, allowing for finer spacing between interconnect points while maintaining reliable electrical connections
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables improved bridge pitch scaling, reduced interconnect physical area, lower assembly costs, and enhanced thermal stability, while maintaining high-density interconnects and power delivery, thus improving overall semiconductor package performance.
Implementation Method 1
the plurality of TGVs conductively couple the plurality of first conductive pads to the plurality of second conductive pads
Implementation Method 2
the plurality of TSVs of the bridge are directly coupled to the plurality of TGVs of the glass patch with a plurality of first solder balls
Implementation Method 3
incorporating a bridge with adhesive bonding
Implementation Method 4
the first encapsulation layer embeds the plurality of dies, the HDP substrate, the plurality of TMVs, the bridge, the plurality of first solder balls, and the glass patch
Data Source
Figure 1
Figure 2A~2B
Figure 2C~2D
AI summary
Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge over a glass patch. The bridge is coupled to the glass patch with an adhesive layer. The semiconductor package also includes a high-density packaging (HDP) substrate over the bridge and the glass patch. The HDP substrate is conductively coupled to the glass patch with a plurality of through mold vias (TMVs). The semiconductor package further includes a plurality of dies over the HDP substrate, and a first encapsulation layer over the TMVs, the bridge, the adhesive layer, and the glass patch. The HDP substrate includes a plurality of conductive interconnects that conductively couple the dies to the bridge and glass patch. The bridge may be an embedded multi-die interconnect bridge (EMIB), where the EMIB is communicatively coupled to the dies, and the glass patch includes a plurality of through glass vias (TGVs).