Glass Co-Packaged PIC-EIC Assembly for Passive Optical Alignment
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Solution Overview
Problem
Current IC packaging technologies face challenges in co-packaging photonic integrated circuits (PIC) and electrical ICs, particularly in high-volume manufacturing, due to unsuitable architectures that result in high optical signal loss and fail to meet compute density requirements for future technologies.
Innovation Solution
The development of a multi-die device structure that electrically and optically interconnects PIC and EIC dies through a substrate routing structure, using a glass preform with optical waveguides and redistribution layers for efficient optical and electrical coupling, enabling higher bandwidth interconnection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If active alignment architecture is used for co-packaging PIC and EIC dies, then optical coupling can be achieved, but manufacturing complexity increases and manufacturing precision requirements become extremely high
Solution Approach 1:
The patent implements preliminary action by pre-defining alignment features directly on the PIC die during fabrication, and pre-forming corresponding alignment structures on the substrate before EIC die attachment. This preliminary preparation eliminates the need for complex active alignment during final assembly, as components are pre-positioned with precise geometric references that guide automatic alignment.
Solution Approach 2:
The patent introduces an intermediary alignment structure that mediates between the PIC die and EIC die. This intermediate layer includes alignment features such as through-holes, recesses, or protrusions that serve as geometric references, enabling passive alignment without requiring complex active alignment systems. The intermediary structure transfers positional information from the substrate to the PIC die, simplifying the overall alignment process.
2Productivity
If conventional co-packaging architectures are used, then manufacturing can be performed, but optical signal loss increases and compute density requirements cannot be met
Solution Approach 1:
The patent transitions from planar two-dimensional packaging to three-dimensional stacked packaging. Multiple EIC dies and PIC dies are vertically stacked on the substrate, utilizing the vertical dimension to increase compute density. This 3D architecture reduces the optical path length between components while maintaining high integration density, thereby reducing optical signal loss and meeting future compute density requirements.
Solution Approach 2:
The patent segments the photonic and electronic functions into separate PIC and EIC dies that are co-packaged on the same substrate. This segmentation allows each die to be optimized for its specific function while being positioned in optimal locations to minimize optical signal loss. The modular segmented architecture enables flexible arrangement of components to achieve both high compute density and low optical loss.
3Productivity
If high-volume manufacturing is targeted, then production efficiency must increase, but manufacturing precision requirements for optical alignment become harder to maintain
Solution Approach 1:
The patent implements self-service alignment where the alignment features are self-aligning through geometric constraints. The through-holes, recesses, or protrusions on the substrate and PIC die automatically guide positioning during attachment, eliminating the need for external active alignment systems. This self-aligning mechanism maintains high precision even in high-volume manufacturing where manual adjustment is not feasible.
Solution Approach 2:
The patent replaces complex mechanical active alignment systems with simple geometric alignment features. Instead of using mechanical adjustment mechanisms, motors, or sensors for alignment, the design uses predetermined geometric references such as aligned holes or protrusions that provide passive mechanical guidance during attachment, enabling high-volume manufacturing with maintained precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the interconnection capabilities between PIC and EIC dies, improving bandwidth and compute density, making it suitable for high-volume manufacturing and future technology requirements.
Implementation Method 1
a glass preform with optical waveguides
Data Source
AI summary
Multi-die packages including both photonic and electric integrated circuit (IC) die interconnected to each other through a routing structure built-up on a glass substrate. A glass preform comprising an optical waveguide may also be attached to the routing structure. A plurality of electrical IC (EIC) die may be arrayed over the routing structure along with a plurality of photonic IC (PIC). Each PIC may be coupled to an optical waveguide within the glass preform. Conductive vias may extend through the glass substrate and be further coupled with a host substrate. The host substrate may comprise glass and an optical waveguide embedded within the glass. A vertical coupler may be attached to the host substrate to optically couple the host substrate to the optical waveguide within the glass preform of the multi-die package. Many of the multi-die packages may be arrayed over a routing structure on the host substrate.


