Glass Substrate Thin Film Capacitors for Power Delivery
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Solution Overview
Problem
Conventional IC packages face challenges in efficiently delivering power due to increased latency and size constraints, as surface-mounted capacitors lengthen power delivery paths and occupy limited space, while building metal-insulator-metal capacitors in dies or substrates often fail to meet capacitance demands.
Innovation Solution
The implementation of a microelectronic assembly with a glass substrate, through-glass vias, and integrated thin film capacitors, which include conductive pillars and dielectric materials to form high-capacitance density structures, reducing package size and improving power delivery efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If surface-mounted capacitors are used on a backside of a die or on a land side of a circuit board, then the IC package can include capacitors for managing power delivery, but the power delivery path length increases causing latency and the available space is limited
Solution Approach 1:
The patent merges the capacitor structure with the substrate by integrating capacitors directly into the substrate layers, combining the substrate's structural function with the capacitor's power storage function. This eliminates the need for separate surface-mounted capacitors and reduces the power delivery path length by placing capacitors closer to the power consumption sources within the substrate itself.
Solution Approach 2:
The patent transitions from surface-mounted (2D) capacitors to multi-layer embedded (3D) capacitors within the substrate. By utilizing multiple substrate layers and vertical stacking, the design achieves higher capacitance density and shorter power delivery paths by moving the capacitor placement from the surface to internal layers, effectively using the third dimension to reduce latency.
2Reliability
If surface-mounted capacitors are used on a backside of a die or on a land side of a circuit board, then the IC package can include capacitors for managing power delivery, but the available space on the die and circuit board is occupied
Solution Approach 1:
The patent merges the capacitor structure with the substrate by integrating capacitors directly into the substrate layers, combining the substrate's structural function with the capacitor's power storage function. This eliminates the need for separate surface-mounted capacitors and reduces the power delivery path length by placing capacitors closer to the power consumption sources within the substrate itself.
3Quantity of substance
If metal-insulator-metal capacitors are built in dies or substrates, then the capacitance density can be increased, but the capacitance demands are not met
Solution Approach 1:
The patent transitions from surface-mounted (2D) capacitors to multi-layer embedded (3D) capacitors within the substrate. By utilizing multiple substrate layers and vertical stacking, the design achieves higher capacitance density and shorter power delivery paths by moving the capacitor placement from the surface to internal layers, effectively using the third dimension to reduce latency.
Solution Approach 2:
The patent employs composite material structures for capacitors, combining conductive layers, dielectric materials, and insulating layers in multi-layer configurations. This composite approach enables higher capacitance density by optimizing the electrical properties of each layer while maintaining mechanical integrity and thermal performance of the substrate.
4Reliability
If the package size is reduced to improve power delivery efficiency, then the capacitance density must be increased, but the structural stability may be affected
Solution Approach 1:
The patent transitions from surface-mounted (2D) capacitors to multi-layer embedded (3D) capacitors within the substrate. By utilizing multiple substrate layers and vertical stacking, the design achieves higher capacitance density and shorter power delivery paths by moving the capacitor placement from the surface to internal layers, effectively using the third dimension to reduce latency.
Data Source
AI summary
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a glass substrate, having a surface, including a through-glass-substrate via (TGV) and a cavity on the surface; a first die nested in the cavity; an insulating material on the surface of the glass substrate; a first conductive pillar and a second conductive pillar through the insulating material; a capacitor, in the insulating material, including a first conductive layer, on the surface of the glass substrate, electrically coupled to the TGV and the first conductive pillar forming a first plate of the capacitor, a dielectric layer on the first conductive layer; and a second conductive layer, on the dielectric layer, electrically coupled to the second conductive pillar forming a second plate of the capacitor; and a second die, on the insulating material, electrically coupled to the first die.