Glass-Substrate Leadless Package for Galvanic Die Isolation
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Solution Overview
Problem
Conventional isolation methods for semiconductor circuits face limitations such as bulkiness, limited bandwidth, susceptibility to environmental factors, and challenges in maintaining creepage and clearance distances, especially in leadless packages, which complicate manufacturing and introduce reliability risks.
Innovation Solution
A package comprising a glass substrate with isolated electrically conductive interconnect route layers, electrically conductive top plates, and an inductive plate for galvanic isolation between semiconductor dies, eliminating the need for external components and coatings, and utilizing glass for environmental protection and structural strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional isolation components (optocouplers, capacitors, transformers) are used, then galvanic isolation is achieved, but the device becomes bulky and complex
Solution Approach 1:
The patent merges the isolation function with the substrate itself by creating a capacitive structure directly in the substrate layer. The substrate is divided into first and second isolation regions with different potential levels, forming a capacitor where the substrate acts as one electrode and a conductive layer forms the other electrode, eliminating the need for separate isolation components.
Solution Approach 2:
The substrate serves multiple functions simultaneously: it provides mechanical support, electrical connection, and galvanic isolation. The same substrate structure that provides physical support also creates the capacitive isolation effect through its layered conductive structure, reducing overall device complexity.
2Reliability
If insulation distance is increased within semiconductor device, then ESD protection is improved, but the device footprint increases
Solution Approach 1:
The patent changes the electrical parameters of the substrate by creating regions with different potential levels. By applying different voltages to different regions of the substrate, the electric field distribution is optimized to provide ESD protection without requiring increased physical spacing between components.
Solution Approach 2:
Instead of increasing isolation distance in the horizontal plane, the patent utilizes the vertical dimension by creating a capacitive structure with electrodes separated in the thickness direction of the substrate. This allows isolation and ESD protection without increasing the device footprint.
3Area of stationary object
If leadless package configuration is used, then footprint is reduced, but manufacturing complexity and reliability risks increase
Solution Approach 1:
The patent combines the isolation structure with the substrate fabrication process itself. The capacitive isolation structure is created using the same semiconductor manufacturing steps that form the substrate, eliminating the need for separate assembly steps and reducing manufacturing complexity despite the leadless configuration.
4Reliability
If creepage and clearance distances are maintained in leadless package, then electrical breakdown is prevented, but available space is reduced
Solution Approach 1:
The patent addresses creepage and clearance requirements by utilizing the vertical dimension through the capacitive substrate structure. The electrical isolation is achieved through the thickness of the substrate and the vertical separation between conductive layers, allowing adequate electrical distances without consuming horizontal space that would be needed in traditional planar isolation approaches.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides robust isolation from external interference, simplifies manufacturing, enhances reliability, and extends longevity by leveraging glass as a substrate material with integrated electromagnetic compatibility measures.
Implementation Method 1
an inductive plate (11) is provided in or at the bottom side of the glass substrate (2), wherein the inductive plate (11) is oriented such that an inductive coupling is provided between: the first electrically conductive plate (7) and the inductive plate (11), and the second electrically conductive plate (8) and the inductive plate (11)
Data Source
AI summary
The present disclosure generally relates to the field of leadless packaging and, more specifically, to leadless packages that include at least two galvanic isolated semiconductor dies and a method of manufacturing such a leadless package.