Glass Packaging Substrate Cavity Layout for Reduced Fill Gaps
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Solution Overview
Problem
Existing semiconductor packaging technologies are limited by high resistivity and dielectric constants in ceramic substrates, and pitch limitations in resin substrates, which hinder the performance of high-frequency semiconductor devices, and there is a need for improved heat dissipation and electrical connections.
Innovation Solution
A packaging substrate using a glass substrate with inclined sidewalls and reduced gaps between cavity elements and sidewalls, filled with insulating and metallic materials, to enhance electrical performance and facilitate layer build-up.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ceramic substrates are used for packaging, then high resistivity and high dielectric constant are achieved, but it becomes difficult to mount high-performance, high-frequency semiconductor devices
Solution Approach 1:
The patent employs a composite substrate structure combining glass substrate with copper foil layers and resin materials. This composite approach achieves low dielectric constant (3.5 or less) and low loss tangent (0.005 or less) while maintaining mechanical strength and thermal stability, enabling high-frequency device mounting without the electrical performance compromises of traditional ceramic substrates
2Adaptability or versatility
If resin substrates are used for packaging, then high-performance, high-frequency semiconductor devices can be mounted, but there are limitations in reducing the pitch of the wiring
Solution Approach 1:
The patent achieves wiring pitch reduction by controlling key parameters: dielectric constant (3.5 or less), loss tangent (0.005 or less), and substrate thickness (30-100 μm). These parameter optimizations enable finer wiring pitch while maintaining signal integrity for high-frequency devices, overcoming the conventional resin substrate limitations
3Reliability
If through-holes are formed in silicon or glass substrate and conductive materials are applied, then wiring between device and motherboard can be shortened with good electrical characteristics, but manufacturing complexity increases
Solution Approach 1:
The patent forms through-holes and applies conductive materials (copper foil, tungsten, or molybdenum) as preliminary structures before final device assembly. This preliminary action shortens the wiring path between device and motherboard, improving electrical characteristics while the standardized process reduces manufacturing complexity
4Ease of manufacture
If cavity part with vertical sidewalls is used, then manufacturing is simpler, but gap volume between sidewall and cavity element is larger causing material loss and surface fluctuations
Solution Approach 1:
The patent employs asymmetric cavity design where the sidewall is inclined at 45-60 degrees relative to the substrate surface, creating a tapered gap that reduces volume compared to vertical sidewalls. This asymmetric geometry minimizes filling material loss and reduces surface fluctuations, while the standardized inclination angle maintains manufacturing simplicity
Data Source
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AI summary
The present disclosure relates to a packaging substrate, a manufacturing method of packaging substrate, and the like. A packaging substrate according to the present disclosure includes a glass substrate having first and second sides facing each other; a cavity part formed in the glass substrate; and a cavity element disposed in the cavity part. The cavity part includes a cavity space in which at least a portion of the cavity element is inserted, a sidewall surrounding the cavity space, and a gap disposed between a first side of the cavity element and the sidewall, the gap being filled with one or more types of filling material. By doing so, the volume for filling the gap between the sidewall of the cavity part and the cavity element can be reduced, and the utilized area of the glass substrate can be increased, the loss of the filling material can be reduced, and the surface fluctuation can be reduced to produce effects that favor the formation of an additional build-up layer.